Inventor · disambiguated record
Vedaraman Geetha
Also filed as: GEETHA VEDARAMAN
34 granted patents·8 pending applications·82 citations·filing 2010–2025
96Inventor score
Top patents by PatentIndex Score
42 records- 0198US11816036B2Method and system for performing data movement operations with read snapshot and in place write updateINTEL CORP·Filed 2022·Granted Nov 14, 2023·11 cites·25 claims
- 0296US12197357B2High performance interconnectINTEL CORP·Filed 2021·Granted Jan 14, 2025·2 cites·20 claims
- 0394US10795853B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2017·Granted Oct 6, 2020·9 cites·24 claims
- 0494US9626321B2High performance interconnectINTEL CORP·Filed 2013·Granted Apr 18, 2017·14 cites·1 claims
- 0593US10248591B2High performance interconnectINTEL CORP·Filed 2016·Granted Apr 2, 2019·5 cites·23 claims
- 0692US11741030B2High performance interconnectINTEL CORP·Filed 2020·Granted Aug 29, 2023·2 cites·20 claims
- 0791US11586579B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2021·Granted Feb 21, 2023·2 cites·24 claims
- 0890US2025321910A1High performance interconnectINTEL CORP·Filed 2025·Application pending·0 cites
- 0989US10606755B2Method and system for performing data movement operations with read snapshot and in place write updateINTEL CORP·Filed 2017·Granted Mar 31, 2020·5 cites·21 claims
- 1089US9619396B2Two level memory full line writesINTEL CORP·Filed 2015·Granted Apr 11, 2017·6 cites·24 claims
- 1187US11327894B2Method and system for performing data movement operations with read snapshot and in place write updateINTEL CORP·Filed 2020·Granted May 10, 2022·2 cites·9 claims
- 1285US12189550B2High performance interconnectINTEL CORP·Filed 2023·Granted Jan 7, 2025·0 cites·20 claims
- 1384US11741028B1Efficiently striping ordered PCIe writes across multiple socket-to-socket linksQUALCOMM INC·Filed 2022·Granted Aug 29, 2023·1 cites·24 claims
- 1483US9418009B2Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memoryINTEL CORP·Filed 2013·Granted Aug 16, 2016·7 cites·21 claims
- 1583US8392665B2Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache linesMOGA ADRIAN C·Filed 2010·Granted Mar 5, 2013·12 cites·30 claims
- 1678US2025225090A1High performance interconnectINTEL CORP·Filed 2025·Application pending·0 cites
- 1776US11899615B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2023·Granted Feb 13, 2024·0 cites·24 claims
- 1874US11269793B2High performance interconnectINTEL CORP·Filed 2020·Granted Mar 8, 2022·0 cites·21 claims
- 1971US10140213B2Two level memory full line writesINTEL CORP·Filed 2017·Granted Nov 27, 2018·1 cites·24 claims
- 2071US2019391939A1High performance interconnectINTEL CORP·Filed 2019·Application pending·0 cites
- 2170US11789645B2Methods and systems for memory bandwidth controlQUALCOMM INC·Filed 2023·Granted Oct 17, 2023·0 cites·20 claims
- 2269US11829637B2Methods and systems for memory bandwidth controlQUALCOMM INC·Filed 2023·Granted Nov 28, 2023·0 cites·18 claims
- 2365US11294852B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2020·Granted Apr 5, 2022·0 cites·25 claims
- 2465US9606925B2Method, apparatus and system for optimizing cache memory transaction handling in a processorINTEL CORP·Filed 2015·Granted Mar 28, 2017·1 cites·20 claims
- 2564US2015081984A1High performance interconnect coherence protocolINTEL CORP·Filed 2014·Application pending·0 cites
- 2663US9405687B2Method, apparatus and system for handling cache misses in a processorINTEL CORP·Filed 2013·Granted Aug 2, 2016·2 cites·22 claims
- 2763US2017109286A1High performance interconnect coherence protocolINTEL CORP·Filed 2016·Application pending·0 cites
- 2855US10042562B2Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory deviceINTEL CORP·Filed 2017·Granted Aug 7, 2018·0 cites·20 claims
- 2953US8631210B2Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache linesINTEL CORP·Filed 2013·Granted Jan 14, 2014·0 cites·20 claims
- 3052US11899964B2Methods and systems for memory bandwidth controlQUALCOMM INC·Filed 2022·Granted Feb 13, 2024·0 cites·20 claims
- 3152US9747041B2Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory deviceINTEL CORP·Filed 2015·Granted Aug 29, 2017·0 cites·25 claims
- 3250US9436605B2Cache coherency apparatus and method minimizing memory writeback operationsINTEL CORP·Filed 2013·Granted Sep 6, 2016·0 cites·19 claims
- 3347US11669454B2Hybrid directory and snoopy-based coherency to reduce directory update overhead in two-level memoryINTEL CORP·Filed 2019·Granted Jun 6, 2023·0 cites·24 claims
- 3447US10514990B2Mission-critical computing architectureINTEL CORP·Filed 2017·Granted Dec 24, 2019·0 cites·25 claims
- 3547US10007606B2Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memoryINTEL CORP·Filed 2016·Granted Jun 26, 2018·0 cites·21 claims
- 3645US10782729B2Clock signal modulation for processorsINTEL CORP·Filed 2017·Granted Sep 22, 2020·0 cites·20 claims
- 3745US10379768B2Selective memory mode authorization enforcementINTEL CORP·Filed 2016·Granted Aug 13, 2019·0 cites·23 claims
- 3841US2014281270A1Mechanism to improve input/output write bandwidth in scalable systems utilizing directory based coherecyNEEFS HENK G·Filed 2013·Application pending·0 cites
- 3939US10204049B2Value of forward state by increasing local caching agent forwardingGEETHA VEDARAMAN·Filed 2012·Granted Feb 12, 2019·0 cites·20 claims
- 4039US8495091B2Dynamically routing data responses directly to requesting processor coreBAUM ALLEN J·Filed 2011·Granted Jul 23, 2013·0 cites·20 claims
- 4138US2013007376A1Opportunistic snoop broadcast (osb) in directory enabled home snoopy systemsKOTTAPALLI SAILESH·Filed 2011·Application pending·0 cites
- 4233US2017185515A1Cpu remote snoop filtering mechanism for field programmable gate arrayFAHIM BAHAA·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →