Inventor

CHANG KUEN-LONG

TW142 patents

⚠️ This page may combine multiple inventors who share the name “CHANG KUEN-LONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG KUEN-LONG

MACRONIX INT CO LTD

Memory and method for checking reading errors thereof

Regulator system for charge pump circuits

Write protected, non-volatile memory device with user programmable sector lock capability

Memory cell sense amplifier

Method and system for soft programming algorithm

Physical unclonable function for non-volatile memory

Method and system for a serial peripheral interface

On chip voltage generation for low power integrated circuits

Power saving buffer circuit buffer bias voltages

Block-level wordline enablement to reduce negative wordline stress

Rapid on chip voltage generation for low power integrated circuits

Non-volatile memory with physical unclonable function and random number generator

Physical unclonable function for security key

Physical unclonable function for non-volatile memory

Non-volatile memory with security key storage

Physical unclonable function using divided threshold distributions in non-volatile memory

Retention logic for non-volatile memory

Multi-level memory cell programming methods

Dynamic program and read adjustment for multi-level cell memory array

Multi-level-cell programming methods of non-volatile memories

Address transition detection circuit for a semiconductor memory capable of detecting narrowly spaced address changes

Double programming methods of a multi-level-cell nonvolatile memory

Multi-level-cell programming methods of non-volatile memories

PUF applications in memories

PUF applications in memories

Method and system for enhanced read performance in low pin count interface

Write-while-read access method for a memory device

Memory and method for operating a memory with interruptible command sequence

Device and method for detecting controller signal errors in flash memory

ECC method for flash memory

Method and apparatus for the erase suspend operation

Memory devices with data protection

Output pad precharge circuit for semiconductor devices

Method and system for a serial peripheral interface

Power source for memory circuitry

Stabilization of output timing delay

Memory system and a voltage regulator

Power drop detector circuit and operating method of same

HUNG CHUN-HSIUNG

Method and apparatus for shortened erase operation

Method and system for a serial peripheral interface

Method and system for a serial peripheral interface

Method and system for enhanced read performance in serial peripheral interface

NAT SCIENCE COUNCIL OF R O C

Charge pumping circuit having cascaded stages receiving two clock signals

LIN YUNG FENG

Twisted data lines to avoid over-erase cell result coupling to normal cell result

LEE CHUN-YI

Method and apparatus for reducing erase time of memory by using partial pre-programming

HUNG CHUN HSIUNG

Method and apparatus for reducing erase disturb of memory by using recovery bias

CHANG YI-FAN

Method and apparatus of performing an erase operation on a memory integrated circuit

CHAUNG YU-MENG

Self-calibration of output buffer driving strength

CHANG CHIN-HUNG

Memory device and read operation method thereof

YU CHUAN-YING

Method and apparatus for the erase suspend operation