Memory device and read operation method thereof

Abstract

A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current.

What is claimed is: 
     
       1. A read operation method for a memory device, the method comprising:
 in response to an input address indicating to read data from a different page, precharging a selected word line of an array cell, a first global bit line group, a second global bit line group and a selected first bit line group; 
 generating a first cell current flowing through the array cell, the first global bit line group and the selected first bit line group, and generating a first reference current flowing through the second global bit line group; 
 reading a first half page data based on the first cell current and the first reference current; 
 keeping the selected word line, the first global bit line group and the second global bit line group in a precharged state; 
 generating a second cell current flowing through the array cell, and generating a second reference current; and 
 reading a second half page data based on the second cell current and the second reference current. 
 
     
     
       2. The read operation method according to  claim 1 , wherein in sensing the second half page data, the second cell current further flows through the array cell, a selected second bit line group and the second global bit line group; and the first global bit line group is as a loading for the second reference current. 
     
     
       3. The read operation method according to  claim 2 , further comprising:
 after the first half page data is latched, a selected second bit line group is precharged and the selected first bit line group is discharged. 
 
     
     
       4. The read operation method according to  claim 1 , wherein in sensing the second half page data, the second cell current further flows through the array cell, the selected first bit line group and the first global bit line group; and the second global bit line group is as a loading for the second reference current. 
     
     
       5. The read operation method according to  claim 1 , wherein in sensing the second half page data, the second cell current further flows through the array cell, the selected first bit line group and the first global bit line group; and the second global bit line group is as a loading for the second reference current. 
     
     
       6. The read operation method according to  claim 5 , wherein in sensing the first half page data and the second half page data, the selected first bit line group is kept in a precharge state. 
     
     
       7. A memory device, including:
 an array cell; 
 a first global bit line group; 
 a second global bit line group; 
 a first bit line selector, coupled to the array cell, for selectively coupling the first global bit line group to the array cell; 
 a second bit line selector, coupled to the array cell, for selectively coupling the second global bit line group to the array cell; and 
 a sensing amplifier circuit, coupled to the first and the second bit line selectors; 
 wherein if the memory device receives an input address indicating to read data from a different page, 
 in sensing a first half page data, the first bit line selector is selected so that a selected word line of the array cell, the first global bit line group, the second global bit line group and a selected first bit line group are precharged by the sensing amplifier circuit to generate a first cell current flowing through the array cell, the first global bit line group and the selected first bit line group and to generate a first reference current flowing through the second global bit line group, and the sensing amplifier circuit reading the first half page data based on the first cell current and the first reference current; 
 the sensing amplifier circuit keeping the selected word line, the first global bit line group and the second global bit line group in a precharged state; 
 in sensing a second half page data, the sensing amplifier circuit generating a second cell current flowing through the array cell and generating a second reference current, and the sensing amplifier circuit reading the second half page data based on the second cell current and the second reference current. 
 
     
     
       8. The memory device according to  claim 7 , wherein in sensing the second half page data, the second bit line selector is selected so that the sensing amplifier circuit generating the second cell current further flowing through the array cell, a selected second bit line group and the second global bit line group, and the first global bit line group is as a loading for the second reference current. 
     
     
       9. The memory device according to  claim 8 , wherein after the first half page data is latched by the sensing amplifier circuit, the second bit line selector is selected so that a selected second bit line group is precharged and the selected first bit line group is discharged. 
     
     
       10. The memory device according to  claim 7 , wherein in sensing the second half page data, the first bit line selector is selected so that the sensing amplifier circuit generating the second cell current further flowing through the array cell, the selected first bit line group and the first global bit line group; and the second global bit line group is as a loading for the second reference current. 
     
     
       11. The memory device according to  claim 7 , wherein in sensing the second half page data, the first bit line selector is selected so that the sensing amplifier circuit generating the second cell current further flowing through the array cell, the selected first bit line group and the first global bit line group; and the second global bit line group is as a loading for the second reference current. 
     
     
       12. The memory device according to  claim 11 , wherein in sensing the first half page data and the second half page data, the first bit line selector is selected so that the selected first bit line group is kept in a precharge state.