Inventor

NOWAK EDWARD JOSEPH

US47 patents

⚠️ This page may combine multiple inventors who share the name “NOWAK EDWARD JOSEPH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NOWAK EDWARD JOSEPH

IBM

High-voltage high-speed SOI MOSFET

Double SOI device with recess etch and epitaxy

FET with T-shaped gate

Voltage translation circuit for mixed voltage applications

Semiconductor structure incorporating thin film transistors with undoped cap oxide layers

Switched body SOI (silicon on insulator) circuits and fabrication method therefor

Semiconductor structure incorporating thin film transistors, and methods for its manufacture

Antifuse circuit using standard MOSFET devices

Dense chevron finFET and method of manufacturing same

Method of forming fet with T-shaped gate

Semiconductor device including back-gated transistors and method of fabricating the device

Semiconductor device with decoupling capacitance

Leak tolerant low power dynamic circuits

Apparatus for biasing ultra-low voltage logic circuits

Self-regulating voltage divider for series-stacked voltage rails

Antifuse circuit using standard MOSFET devices

Method of making contacted body silicon-on-insulator field effect transistor

Transistors having asymmetric strained source/drain portions

Semiconductor transistors with expanded top portions of gates

Formation of spacers for FinFETs (Field Effect Transistors)

Spacers for FinFETs (Field Effect Transistors)

Serial irradiation of a substrate by multiple radiation sources

Domino logic circuit having multiplicity of gate dielectric thicknesses

Method of forming semiconductor device with decoupling capacitance

Dynamic threshold voltage devices with low gate to substrate resistance

Dynamic threshold voltage devices with low gate to substrate resistance

Serial irradiation of a substrate by multiple radiation sources

Methods of changing threshold voltages of semiconductor transistors by ion implantation

Transistors having asymmetric strained source/drain portions

System for and method of verifying IC authenticity

Simultaneous irradiation of a substrate by multiple radiation sources

Radiation mask with spatially variable transmissivity

Field effect transistor with thin gate electrode and method of fabricating same

Integrated circuit with anti-counterfeiting measures

Field effect transistor with thin gate electrode and method of fabricating same

Methods for reducing within chip device parameter variations

Method for reducing within chip device parameter variations

Method for fabricating a field effect transistor having a dual thickness gate electrode

Stressed dielectric devices and methods of fabricating same

Stressed dielectric devices and methods of fabricating same

Combination planar FET and FinFET device

Formation of dummy features and inductors in semiconductor fabrication

ANDERSON BRENT ALAN

Semiconductor transistors with expanded top portions of gates

Configuring radiation sources to simultaneously irradiate a substrate

Method of fabricating strained semiconductor structures from silicon-on-insulator (SOI)

GLOBALFOUNDRIES INC

Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same

BEINTNER JOCHEN

Dense chevron finFET and method of manufacturing same