Method for fabricating a field effect transistor having a dual thickness gate electrode

Abstract

A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

1. A method of fabricating a field effect transistor, comprising:
 forming a dielectric isolation along an entire perimeter of a region of a silicon layer to define a silicon body in said silicon layer; 
 forming a gate dielectric layer on said silicon body, said gate dielectric layer having a single thickness; 
 forming an electrically conductive gate electrode on said gate dielectric layer, said gate dielectric layer having a uniform thickness after said forming said electrically conductive gate electrode, a bottom surface of said gate electrode abutting a top surface of said gate dielectric layer, said gate electrode having a first region having a first thickness and a second region having a second thickness, said first region extending along said top surface of said gate dielectric layer over a channel region of said silicon body, said second thickness greater than said first thickness; and 
 wherein a bottom surface of an insulating layer abuts a bottom surface of said silicon body, said bottom surface of said silicon body opposite a top surface of said silicon body. 
 
     
     
       2. The method of  claim 1 , wherein said forming said gate electrode includes:
 forming a polysilicon layer on said top surface of said gate dielectric layer; 
 patterning said polysilicon layer to form a patterned polysilicon layer; 
 oxidizing a less than whole thickness of a region of said patterned polysilicon layer over said silicon body to form an oxidized region of said patterned polysilicon layer; 
 after forming a source and a drain, removing said oxidized region of said patterned polysilicon layer to form a thinned region of said patterned polysilicon layer and a thick region of said patterned polysilicon layer; and 
 simultaneously (i) entirely converting said thinned region of said patterned polysilicon layer to a metal silicide layer and (ii) converting a less than whole thickness of said thick region of said patterned polysilicon layer to a metal silicide layer. 
 
     
     
       3. The method of  claim 2 , further including:
 before (i) and (ii), forming a dielectric spacer on sidewalls of said electrically conductive gate electrode. 
 
     
     
       4. The method of  claim 1 , wherein said forming said gate electrode includes:
 forming a metal layer on said top surface of said gate dielectric layer; 
 patterning said metal layer; 
 etching away a less than whole thickness of said metal layer in a region of said metal layer over said silicon body to form said first region of said electrically conductive gate electrode; 
 forming a dielectric layer over said first region of said electrically conductive gate electrode; and 
 after forming said source and said drain, removing said dielectric layer. 
 
     
     
       5. The method of  claim 1 , wherein a top surface of said second region of said electrically conductive gate electrode is further away from said top surface of said gate dielectric layer than a top surface of said first region of said electrically conductive gate electrode is away from said top surface of said gate dielectric layer. 
     
     
       6. The method of  claim 1 , wherein said second region does not overlap said silicon body. 
     
     
       7. The method of  claim 1 , wherein said second region overlaps at least a region of said silicon body. 
     
     
       8. The method of  claim 1 , wherein said first thickness is less than or equal to about 40 nm. 
     
     
       9. The method of  claim 1 , wherein a channel length of said field effect transistor is defined by a width of said electrically conductive gate electrode between a source and a drain formed in said silicon body, and wherein said first thickness divided by said channel length is less than or equal to one. 
     
     
       10. The method of  claim 1 , wherein a channel length of said field effect transistor is defined by a width of said electrically conductive gate electrode between a source and a drain formed in said silicon body, and wherein said channel length is greater than or equal to four times said first thickness. 
     
     
       11. The method of  claim 1 , further including:
 forming an insulating layer on said electrically conductive gate electrode; and 
 forming a gate electrode contact through said insulating layer, said gate electrode contact in direct physical and electrical contact only with said second region of said gate electrode and said insulating layer. 
 
     
     
       12. The method of  claim 1 , wherein a top surface of a semiconductor layer abuts a bottom surface of said insulating layer, said bottom surface of said insulating layer opposite a top surface of said insulating layer. 
     
     
       13. The method of  claim 1 , further including:
 forming a gate electrode contact to said second region of said gate electrode, said gate electrode contact only in physical contact with said second region of said gate electrode. 
 
     
     
       14. The method of  claim 1 , wherein said gate dielectric layer is a high dielectric constant material. 
     
     
       15. The method of  claim 1 , wherein said gate dielectric layer comprises one or more metal oxides, one or more metal silicates or combinations of layers thereof. 
     
     
       16. The method of  claim 1 , wherein said gate dielectric layer comprises Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , HfSi x O y HfSi x O y N z  or combinations thereof. 
     
     
       17. A method of forming a field effect transistor, comprising:
 forming, in a silicon layer, a source and a drain on opposite sides of a channel region; 
 forming a metal or metal silicide gate electrode having an electrode region and a raised contact region, said raised contact region thicker than said electrode region, said electrode region having a thickness of less than or equal to 40 nanometers; 
 forming a gate dielectric layer between said metal or metal silicide gate electrode and said channel region; and 
 wherein a length of said channel region measured perpendicularly between said source and drain is at least four times a thickness of said electrode region. 
 
     
     
       18. The method of  claim 17 , wherein said raised contact region does not overlap said channel region. 
     
     
       19. The method of  claim 17 , wherein said raised contact region overlaps a less than whole portion of said channel region.