Inventor

YE YIBIN

US86 patents

⚠️ This page may combine multiple inventors who share the name “YE YIBIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YE YIBIN

INTEL CORP

Floating-body memory cell write

Floating-body DRAM using write word line for increased retention time

Purge-based floating body memory

OTP antifuse cell and cell array

System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise

SRAM array with dynamic voltage for reducing active leakage power

Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode

Method and apparatus for reducing standby leakage current using a transistor stack effect

Method and apparatus to clamp SRAM supply voltage

Dual threshold SRAM cell for single-ended sensing

Dual Vt SRAM cell with bitline leakage control

Memory having bit line with resistor(s) between memory cells

Memory with dynamically adjustable supply

2-transistor floating-body dram

Method and apparatus to clamp SRAM supply voltage

Reducing power consumption in integrated circuits

Dual gate oxide one time programmable (OTP) antifuse cell

Systolic memory arrays

Apparatus and method for programming a memory array

1P1N 2T gain cell

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Stable memory cell read

Method and apparatus for leakage compensation with full Vcc pre-charge

Apparatus and method for a memory storage cell leakage cancellation scheme

Reducing leakage currents in integrated circuits

Domino logic with low-threshold NMOS pull-up

Domino logic circuit and method

Method and apparatus for reducing standby leakage current using input vector activation

Method and apparatus for generating waveforms using adiabatic circuitry

Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency

Method and apparatus for reducing signal transmission delay using skewed gates

NMOS precharge domino logic

Dual-level voltage shifters for low leakage power

Memory circuit

Memory cell driver circuits

Two transistor gain cell, method, and system

Crosspoint memory array utilizing one time programmable antifuse cells

Apparatus and method for a one-phase write to a one-transistor memory cell array

Floating-body DRAM using write word line for increased retention time

Memory cell leakage reduction

Domino logic circuit and method

SRAM with forward body biasing to improve read cell stability

Memory cell bit valve loss detection and restoration

Non volatile data storage through dielectric breakdown

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

SRAM cell power reduction circuit

Majority voter apparatus, systems, and methods

Overvoltage detection apparatus, method, and system

KHELLAH MUHAMMAD

Memory cell supply voltage control based on error detection

SOMASEKHAR DINESH

Multi-die integrated circuit device and method