System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise

Abstract

A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.

What is claimed is:  
     
       1. A system, comprising: 
       a first sleep transistor to control the application of power to at least one circuit and to receive a sleep transistor control signal;  
       a second sleep transistor to control application of power to the at least one circuit and to receive a complement of the sleep transistor control signal; and  
       a region formed in a body of the first sleep transistor and adapted to receive a body bias voltage to alter operational characteristics of the first sleep transistor, wherein the first sleep transistor is turned off in response to the absence of a sleep control signal or a sleep control signal that turns off the first sleep transistor and wherein the region to selectively receive a reverse biased voltage to substantially reduce power consumption due to leakage current drawn by the at least one circuit.  
     
     
       2. The system of  claim 1 , wherein the leakage current is inversely proportional to the reverse body bias voltage applied to the first sleep transistor. 
     
     
       3. The system of  claim 1 , wherein the first transistor is a P channel metal oxide semiconductor (PMOS) transistor and the second transistor is an N channel metal oxide semiconductor (NMOS) transistor. 
     
     
       4. The system of  claim 1 , further comprising a body bias voltage generator adapted to provide the body bias voltage and wherein the body bias voltage generator comprises: 
       a voltage translator coupled to a reference voltage and a supply voltage; and  
       a voltage buffer coupled to the voltage translator.  
     
     
       5. The system of  claim 1 , further comprising a sleep controller coupled to the first and second sleep transistors. 
     
     
       6. A method, comprising: 
       controlling the operation of a switching device to control the application of power to a circuit;  
       applying one of a forward body bias voltage, a zero body bias voltage or a reverse body bias voltage to a region formed in a body of the switching device to enhance the operating characteristics of the switching device;  
       disconnecting the power from the circuit in response to the switching device receiving a predetermined control signal; and  
       applying a predetermined reverse body bias voltage to the region to substantially reduce the flow of any leakage current through the switching device.  
     
     
       7. The method of  claim 6 , further comprising: 
       connecting the power to the circuit in response to the switching device receiving a predetermined sleep control signal; and  
       applying a predetermined forward body biased voltage to the region to enhance the operational characteristics of the switching device and to substantially reduce a performance penalty of the switching device and substantially reduce adverse noise effects on the circuit.  
     
     
       8. The method of  claim 6 , further comprising: 
       reducing the effective threshold voltage for operation of the switching device;  
       increasing a current drive of the switching device;  
       decreasing a voltage drop across the switching device; and  
       increasing a speed of operation of the switching device and the circuit, all by applying a predetermined forward body biased voltage level to the switching device.  
     
     
       9. The method of  claim 8 , wherein the predetermined forward body biased voltage is applied so that the body of the switching device is at a lower voltage potential than a power supply voltage. 
     
     
       10. The method of  claim 6 , further comprising: 
       controlling the operation of another switching device with a control signal to turn the other snitching device on and off.  
     
     
       11. The method of  claim 10 , wherein the one switching device is a P channel metal oxide semiconductor (PMOS) sleep transistor and the other switching device is an N channel metal oxide semiconductor (NMOS) sleep transistor. 
     
     
       12. The method of  claim 10 , wherein the one switching device is an N channel metal oxide semiconductor (NMOS) sleep transistor and the other switching device is a P channel metal oxide semiconductor (PMOS) sleep transistor. 
     
     
       13. A method, comprising: 
       controlling the operation of a switching device to control the application of power to a circuit;  
       applying one of a forward body bias voltage, a zero body bias voltage or a reverse body bias voltage to a region formed in a body of the switching device to enhance the operating characteristics of the switching device;  
       disconnecting the power from the circuit in response to the switching device receiving a predetermined control signal; and  
       applying a predetermined reverse body bias voltage to the region to cause the body of the switching device to be at a higher voltage potential than a power supply voltage.  
     
     
       14. The method of  claim 13 , further comprising connecting a body bias voltage to the region to apply the forward body bias voltage, the zero body bias voltage or the reverse body bias voltage. 
     
     
       15. The method of  claim 13 , further comprising connecting a processor to a body bias voltage generator to control the body bias voltage applicable to the one switching device. 
     
     
       16. The method of  claim 13 , further comprising providing a processor to generate control signals to control operation of the switching device to either connect the power to the circuit or to disconnect the power from the circuit. 
     
     
       17. A method, comprising: 
       controlling the operation of a switching device to control the application of power to a circuit;  
       applying one of a forward body bias voltage, a zero body bias voltage or a reverse body bias voltage to a region formed in a body of the switching device to enhance the operating characteristics of the switching device;  
       connecting the power to the circuit in response to the switching device receiving a predetermined sleep control signal; and  
       applying a predetermined forward body biased voltage to the region to enhance the operational characteristics of the switching device and to substantially reduce a performance penalty of the switching device and substantially reduce adverse noise effects on the circuit.