Inventor

HAMZAOGLU FATIH

US42 patents

⚠️ This page may combine multiple inventors who share the name “HAMZAOGLU FATIH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAMZAOGLU FATIH

INTEL CORP

Dual threshold SRAM cell for single-ended sensing

Memory with dynamically adjustable supply

Dynamic multi-Vcc scheme for SRAM cell stability control

Apparatus and method for a memory storage cell leakage cancellation scheme

Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength

Apparatuses and methods to control operations performed on resistive memory cells

Apparatuses and methods for detecting write completion for resistive memory

Apparatus and method for a memory storage cell leakage cancellation scheme

Memory cells based on vertical thin-film transistors

Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory

Cache leakage shut-off mechanism

Two transistor memory cell using stacked thin-film transistors

Memory cell with improved write margin

Apparatus for adjusting supply level to improve write margin of a memory cell

Noise reduction circuit

Decoupling capacitors and methods of fabrication

Semiconductor chip manufacturing process for integrating logic circuitry, embedded DRAM and embedded non-volatile ferroelectric random access memory (FERAM) on a same semiconductor die

Resistive memory write circuitry with bit line drive strength based on storage cell line resistance

Capacitor connections in dielectric layers

Capacitor separations in dielectric layers

Capacitor connections in dielectric layers

Memory architecture at back-end-of-line

Capacitor separations in dielectric layers

Apparatus for low power write and read operations for resistive memory

Apparatus for low power write and read operations for resistive memory

Backend memory with air gaps in upper metal layers

Bilayer memory stacking with lines shared between bottom and top memory layers

Stacked thin-film transistor based embedded dynamic random-access memory

Reduced read delay for single-ended sensing

Apparatus for low power write and read operations for resistive memory

Resistive memory write circuitry with bit line drive strength based on storage cell line resistance

Memory cell with retention using resistive memory

Intermediate separation layers at the back-end-of-line

WANG YIH

Memory cell with improved write margin

Non-volatile latch using spin-transfer torque memory device

GHOSH SWAROOP

Nor logic word line selection

NAND logic word line selection

DRAY CYRILLE

Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory

KOLAR PRAMOD

Adaptive and dynamic stability enhancement for memories

SOMASEKHAR DINESH

Hierarchical DRAM sensing

RAYCHOWDHURY ARIJIT

Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read current

CHANG TSUNG-YUNG

Bitline floating during non-access mode for memory arrays