Hierarchical DRAM sensing

Abstract

A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.

What is claimed is: 
     
       1. A DRAM with hierarchical sensing, the DRAM comprising:
 a pair of global bit lines (GBLs) extending between a plurality of subarrays, the GBLs terminating in a global sense amp; 
 a cluster of subarray sense amps (SSAs) in each subarray, each SSA having a pair of local bit lines coupled to memory cells, wherein the memory cells are selected by word lines extending to all the memory cells in the cluster; and 
 local precharging circuit associated with each pair of local bit lines, 
 wherein each cluster being controlled such that a single word line is selected throughout the cluster and each SSA in the cluster is enabled during a read cycle, and wherein only one pair of local bit lines from the cluster is coupled to the GBLs. 
 
     
     
       2. The DRAM of  claim 1 , including:
 equalization circuit associated with each pair of local bit lines, and 
 global precharging and equalization circuits associated with the GBLs, wherein the local bit lines are precharged to a potential less than the potential to which the GBLs are precharged. 
 
     
     
       3. The DRAM of  claim 1 , wherein the local bit lines are precharged to a potential of approximately one-half the potential to which the GBLs are precharged. 
     
     
       4. The DRAM of  claim 2 , wherein the local precharging and equalization circuits comprise both p-channel and n-channel transistors. 
     
     
       5. The DRAM of  claim 2 , wherein the local precharging and equalization circuits include both p-channel and n-channel transistors, and wherein the local bit lines are charged to a potential slightly larger than the sum of the threshold voltages of a p-channel and n-channel transistors. 
     
     
       6. A memory having a plurality of banks wherein the DRAM of  claim 1  comprises a single bank in the memory. 
     
     
       7. The memory of  claim 6 , including:
 a plurality of clusters of SSAs in each subarray, 
 a plurality of GBLs, and 
 a plurality of global sense amplifiers. 
 
     
     
       8. A method of sensing in a DRAM, the method comprising:
 precharging to a first potential a plurality of local bit line pairs each associated with a sense amplifier; 
 precharging a pair of global bit lines (GBLs) to a second potential, greater than the first potential; 
 sensing the binary state stored on memory cells selectively coupled to the local bit line pairs with local sense amplifiers; 
 coupling one of the plurality of local bit line pairs to the GBLs; 
 sensing the binary state on the GBLs with a global sense amplifier; and 
 isolating the GBLs from the local bit lines, during precharging of the global sense amplifier. 
 
     
     
       9. The method of  claim 8 , wherein the second potential is approximately equal to twice the first potential. 
     
     
       10. The method of  claim 8 , including restoring the sensed binary state to the selected memory cells. 
     
     
       11. The method of  claim 8 , including floating outputs of a write buffer coupled to the GBLs during the sensing of the binary state on the GBLs. 
     
     
       12. The method of  claim 8 , including interlocking a local precharge and equalization signal and a local sense amplifier enable signal so that precharging and equalization is prevented when sensing is occurring in the local sense amplifier. 
     
     
       13. The method of  claim 8 , including interlocking a global precharge and equalization signal and a global sense amplifier enable signal so that precharging and equalization is prevented when sensing is occurring in the global sense amplifier. 
     
     
       14. A method for sensing in a CMOS DRAM which operates from an applied potential of Vcc, the method comprising:
 precharging a plurality of local bit line pairs each associated with a sense amplifier to a potential of approximately one-half Vcc; 
 precharing a pair of global bit lines (GBLs) to Vcc; 
 initiating sensing of a binary state on the plurality of local bit line pairs with the sense amplifiers; 
 coupling one of the plurality of local bit line pairs to the GBLs; and 
 isolating the local bit lines from the GBLs as sensing occurs in a global sense amplifier. 
 
     
     
       15. The method defined by  claim 14 , wherein Vcc is approximately equal to the sum of the threshold voltages of a p-channel and n-channel transistor used in the CMOS DRAM. 
     
     
       16. The method of  claim 14 , including activating an equalization circuit comprising both n-channel and p-channel transistors during the precharging of the local bit line pairs. 
     
     
       17. The method of  claim 14 , including restoring the sensed binary states to the memory cells selectively coupled to the local bit line pairs. 
     
     
       18. The method defined by  claim 14 , wherein sensing the binary state stored on memory cells comprises selecting a word line which activates the memory cells in the local sense amplifiers. 
     
     
       19. The method of  claim 14 , including isolating the global sense amplifier from the section of the GBLs coupled to the local bit line pairs during precharging of the global sense amplifier.