Inventor · disambiguated record
Fatih Hamzaoglu
Also filed as: HAMZAOGLU FATIH
41 granted patents·8 pending applications·278 citations·filing 2000–2023
97Inventor score
Top patents by PatentIndex Score
49 records- 0194US7403426B2Memory with dynamically adjustable supplyINTEL CORP·Filed 2005·Granted Jul 22, 2008·36 cites·12 claims
- 0292US12238913B2Two transistor memory cell using stacked thin-film transistorsINTEL CORP·Filed 2023·Granted Feb 25, 2025·1 cites·26 claims
- 0390US10515697B1Apparatuses and methods to control operations performed on resistive memory cellsINTEL CORP·Filed 2018·Granted Dec 24, 2019·12 cites·24 claims
- 0490US6519176B1Dual threshold SRAM cell for single-ended sensingINTEL CORP·Filed 2000·Granted Feb 11, 2003·57 cites·21 claims
- 0588US8451670B2Adaptive and dynamic stability enhancement for memoriesKOLAR PRAMOD·Filed 2010·Granted May 28, 2013·14 cites·20 claims
- 0687US7079426B2Dynamic multi-Vcc scheme for SRAM cell stability controlINTEL CORP·Filed 2004·Granted Jul 18, 2006·46 cites·20 claims
- 0786US9865322B2Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memoryINTEL CORP·Filed 2016·Granted Jan 9, 2018·4 cites·20 claims
- 0884US9478273B2Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memoryDRAY CYRILLE·Filed 2013·Granted Oct 25, 2016·8 cites·19 claims
- 0982US12310001B2Decoupling capacitors and methods of fabricationINTEL CORP·Filed 2021·Granted May 20, 2025·1 cites·20 claims
- 1079US9286976B2Apparatuses and methods for detecting write completion for resistive memoryINTEL CORP·Filed 2014·Granted Mar 15, 2016·7 cites·20 claims
- 1179US9111600B2Memory cell with improved write marginWANG YIH·Filed 2012·Granted Aug 18, 2015·5 cites·15 claims
- 1278US9455011B2Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read currentRAYCHOWDHURY ARIJIT·Filed 2012·Granted Sep 27, 2016·6 cites·20 claims
- 1378US8406073B1Hierarchical DRAM sensingSOMASEKHAR DINESH·Filed 2010·Granted Mar 26, 2013·8 cites·19 claims
- 1476US11462541B2Memory cells based on vertical thin-film transistorsINTEL CORP·Filed 2018·Granted Oct 4, 2022·2 cites·21 claims
- 1576US7177176B2Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strengthINTEL CORP·Filed 2004·Granted Feb 13, 2007·23 cites·8 claims
- 1675US12426247B2Capacitor connections in dielectric layersINTEL CORP·Filed 2023·Granted Sep 23, 2025·0 cites·20 claims
- 1773US6608786B2Apparatus and method for a memory storage cell leakage cancellation schemeINTEL CORP·Filed 2001·Granted Aug 19, 2003·18 cites·18 claims
- 1872US7657767B2Cache leakage shut-off mechanismINTEL CORP·Filed 2005·Granted Feb 2, 2010·7 cites·23 claims
- 1967US11991873B2Capacitor separations in dielectric layersINTEL CORP·Filed 2023·Granted May 21, 2024·0 cites·18 claims
- 2065US9978447B2Memory cell with improved write marginINTEL CORP·Filed 2017·Granted May 22, 2018·1 cites·20 claims
- 2164US9281043B1Resistive memory write circuitry with bit line drive strength based on storage cell line resistanceINTEL CORP·Filed 2014·Granted Mar 8, 2016·2 cites·20 claims
- 2260US9666268B2Apparatus for adjusting supply level to improve write margin of a memory cellINTEL CORP·Filed 2015·Granted May 30, 2017·1 cites·14 claims
- 2360US9330747B2Non-volatile latch using spin-transfer torque memory deviceWANG YIH·Filed 2013·Granted May 3, 2016·2 cites·21 claims
- 2458US10068628B2Apparatus for low power write and read operations for resistive memoryINTEL CORP·Filed 2013·Granted Sep 4, 2018·1 cites·9 claims
- 2558US9922691B2Resistive memory write circuitry with bit line drive strength based on storage cell line resistanceINTEL CORP·Filed 2016·Granted Mar 20, 2018·1 cites·16 claims
- 2657US11610894B2Capacitor separations in dielectric layersINTEL CORP·Filed 2019·Granted Mar 21, 2023·0 cites·20 claims
- 2757US6801465B2Apparatus and method for a memory storage cell leakage cancellation schemeINTEL CORP·Filed 2003·Granted Oct 5, 2004·8 cites·41 claims
- 2856US12396155B2Backend memory with air gaps in upper metal layersINTEL CORP·Filed 2021·Granted Aug 19, 2025·0 cites·20 claims
- 2954US11832438B2Capacitor connections in dielectric layersINTEL CORP·Filed 2019·Granted Nov 28, 2023·0 cites·20 claims
- 3054US9805790B2Memory cell with retention using resistive memoryINTEL CORP·Filed 2013·Granted Oct 31, 2017·1 cites·20 claims
- 3154US2025098179A1Memory layers at opposing sides of a complementary metal-oxide semiconductor layerSHARMA ABHISHEK A·Filed 2023·Application pending·0 cites
- 3253US8456946B2NAND logic word line selectionGHOSH SWAROOP·Filed 2010·Granted Jun 4, 2013·1 cites·20 claims
- 3353US2023397410A1Memory device with peripheral circuitry which extends under a back end memory arrayINTEL CORP·Filed 2022·Application pending·0 cites
- 3452US11024356B2Apparatus for low power write and read operations for resistive memoryINTEL CORP·Filed 2019·Granted Jun 1, 2021·0 cites·17 claims
- 3551US10438640B2Apparatus for low power write and read operations for resistive memoryINTEL CORP·Filed 2018·Granted Oct 8, 2019·0 cites·11 claims
- 3650US2025095693A1Connections of bit lines and word lines in stacked memory layers to a complementary metal-oxide-semiconductor layerINTEL CORP·Filed 2023·Application pending·0 cites
- 3749US11690212B2Memory architecture at back-end-of-lineINTEL CORP·Filed 2019·Granted Jun 27, 2023·0 cites·24 claims
- 3846US2023371233A1Multi-tier memory structure with graded characteristicsINTEL CORP·Filed 2022·Application pending·0 cites
- 3945US11652047B2Intermediate separation layers at the back-end-of-lineINTEL CORP·Filed 2019·Granted May 16, 2023·0 cites·19 claims
- 4045US11450669B2Stacked thin-film transistor based embedded dynamic random-access memoryINTEL CORP·Filed 2018·Granted Sep 20, 2022·0 cites·24 claims
- 4145US2020091156A1Two transistor memory cell using stacked thin-film transistorsINTEL CORP·Filed 2018·Application pending·0 cites
- 4242US11094358B2Semiconductor chip manufacturing process for integrating logic circuitry, embedded DRAM and embedded non-volatile ferroelectric random access memory (FERAM) on a same semiconductor dieINTEL CORP·Filed 2016·Granted Aug 17, 2021·0 cites·20 claims
- 4342US2020411635A1Air gaps and capacitors in dielectric layersINTEL CORP·Filed 2019·Application pending·0 cites
- 4441US8982659B2Bitline floating during non-access mode for memory arraysCHANG TSUNG-YUNG·Filed 2009·Granted Mar 17, 2015·2 cites·20 claims
- 4540US6351156B1Noise reduction circuitINTEL CORP·Filed 2000·Granted Feb 26, 2002·2 cites·24 claims
- 4637US6879531B2Reduced read delay for single-ended sensingINTEL CORP·Filed 2002·Granted Apr 12, 2005·1 cites·9 claims
- 4737US2011149667A1Reduced area memory array by using sense amplifier as write driverHAMZAOGLU FATIH·Filed 2009·Application pending·0 cites
- 4836US8547777B2Nor logic word line selectionGHOSH SWAROOP·Filed 2010·Granted Oct 1, 2013·0 cites·20 claims
- 4934US2007153610A1Dynamic body bias with bias boostINTEL CORP·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →