Two transistor memory cell using stacked thin-film transistors

Abstract

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

1 . A memory cell, comprising:
 an access thin-film transistor (TFT); and   a gain TFT;   wherein:
 a first source/drain (S/D) electrode of the access TFT is coupled to a gate electrode of the gain TFT, 
 the access TFT is in a first layer over a substrate, and 
 the gain TFT is in a second layer over the substrate, the first layer being between the substrate and the second layer. 
   
     
     
         2 . The memory cell according to  claim 1 , wherein:
 the access TFT includes a channel material and a second S/D electrode,   the first S/D electrode of the access TFT is over the channel material of the access TFT, and   the channel material of the access TFT is over the second S/D electrode of the access TFT.   
     
     
         3 . The memory cell according to  claim 2 , wherein:
 the gain TFT includes a channel material, a first S/D electrode, and a second S/D electrode,   the gate electrode of the gain TFT is between the substrate and the channel material of the gain TFT, and   the channel material of the gain TFT is between the gate electrode of the gain TFT and the first S/D electrode of the gain TFT and also between the gate electrode of the gain TFT and the second S/D electrode of the gain TFT.   
     
     
         4 . The memory cell according to  claim 2 , wherein the channel material includes one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, indium gallium zinc oxide (IGZO), indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, and black phosphorus. 
     
     
         5 . The memory cell according to  claim 1 , wherein a gate electrode of the access TFT is coupled to a write wordline. 
     
     
         6 . The memory cell according to  claim 1 , wherein a second S/D electrode of the access TFT is coupled to a write bitline. 
     
     
         7 . The memory cell according to  claim 1 , wherein a first S/D electrode of the gain TFT is coupled to a read wordline. 
     
     
         8 . The memory cell according to  claim 1 , wherein a second S/D electrode of the gain TFT is coupled to a read bitline. 
     
     
         9 . The memory cell according to  claim 1 , wherein the first S/D electrode of the access TFT is coupled to the storage node of the memory cell, and the gate electrode of the gain TFT is coupled to the storage node. 
     
     
         10 . The memory cell according to  claim 9 , further comprising a capacitor that includes a first capacitor electrode, a second capacitor electrode, and a dielectric between the first capacitor electrode and the second capacitor electrode, wherein the first capacitor electrode is coupled to the storage node. 
     
     
         11 . The memory cell according to  claim 10 , wherein the second capacitor electrode is coupled to a capacitor plateline. 
     
     
         12 . The memory cell according to  claim 10 , wherein the capacitor is a three-dimensional metal-insulator-metal capacitor. 
     
     
         13 . A memory cell, comprising:
 a substrate;   a first thin-film transistor (TFT) in a back end of line (BEOL) stack above the substrate; and   a second TFT, coupled to the first TFT, in the BEOL stack,   wherein the second TFT is further away from the substrate than the first TFT.   
     
     
         14 . The memory cell according to  claim 13 , wherein the first TFT is a vertical TFT. 
     
     
         15 . The memory cell according to  claim 13 , wherein the second TFT is a horizontal TFT. 
     
     
         16 . The memory cell according to  claim 15 , wherein the horizontal TFT is a horizontal bottom-gated TFT. 
     
     
         17 . The memory cell according to  claim 13 , wherein a first source/drain electrode of the first TFT is coupled to a gate electrode of the second TFT. 
     
     
         18 . The memory cell according to  claim 13 , wherein one or both of the first TFT and the second TFT include a channel material that includes one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, indium gallium zinc oxide (IGZO), indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, and black phosphorus. 
     
     
         19 . A memory array, comprising:
 a plurality of memory cells arranged in rows and columns, individual ones of the memory cells including:
 an access thin-film transistor (TFT), and 
 a gain TFT, 
 wherein:
 a first source/drain (S/D) electrode of the access TFT is coupled to a gate electrode of the gain TFT, 
 the access TFT is in a first layer over a substrate, and 
 the gain TFT is in a second layer over the substrate, the first layer being between the substrate and the second layer; and 
 
   for the memory cells arranged in a row i, a respective write wordline (WWL i ), coupled to a gate electrode of the access TFT of individual ones of the memory cells in the row i.   
     
     
         20 . The memory array according to  claim 19 , further comprising:
 for the memory cells arranged in the row i, a respective read wordline (RWL i ), coupled to a first S/D electrode of the gain TFT of individual ones of the memory cells in the row i.   
     
     
         21 . The memory array according to  claim 19 , wherein:
 individual ones of the memory cells further include a capacitor that includes a first capacitor electrode, a second capacitor electrode, and a dielectric between the first capacitor electrode and the second capacitor electrode, wherein the first capacitor electrode of an individual memory cell is coupled to the first S/D electrode of the access TFT of the individual memory cell; and   the memory array further comprises, for the memory cells arranged in the row i, a respective capacitor plate line (PL i ), coupled to the second capacitor electrode of individual ones of the memory cells in the row i.   
     
     
         22 . The memory array according to  claim 19 , further comprising:
 for the memory cells arranged in a column j, a respective write bitline (WBL j ), coupled to a second S/D electrode of the access TFT of individual ones of the memory cells in the column j.   
     
     
         23 . The memory array according to  claim 19 , further comprising:
 for the memory cells arranged in a column j, a respective read bitline (RBL j ), coupled to a second S/D electrode of the gain TFT of individual ones of the memory cells in the column j.   
     
     
         24 . A computing device, comprising:
 a circuit board; and   a device coupled to the circuit board, wherein the device includes one or more of two-transistor (2T) memory cells, individual ones of the 2T memory cells including:
 an access thin-film transistor (TFT) in a back end of line (BEOL) stack above a substrate, and 
 a gain TFT, coupled to the access TFT, in the BEOL stack, 
 wherein the gain TFT is further away from the substrate than the access TFT. 
   
     
     
         25 . The computing device according to  claim 24 , wherein the computing device is a wearable computing device or handheld computing device.