Inventor

WAN JUN

US126 patents

⚠️ This page may combine multiple inventors who share the name “WAN JUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WAN JUN

SANDISK CORP

Trimming of analog voltages in flash memory devices

Word line compensation in non-volatile memory erase operations

Flash memory devices with trimmed analog voltages

Last-first mode and method for programming of non-volatile memory with reduced program disturb

Last-first mode and apparatus for programming of non-volatile memory with reduced program disturb

System for programming non-volatile memory with self-adjusting maximum program loop

Comprehensive erase verification for non-volatile memory

Word line compensation in non-volatile memory erase operations

Reducing read disturb for non-volatile storage

Reducing read disturb for non-volatile storage

Selective application of program inhibit schemes in non-volatile memory

System for reducing read disturb for non-volatile storage

Comprehensive erase verification for non-volatile memory

Selective program voltage ramp rates in non-volatile memory

Reducing read disturb for non-volatile storage

Reducing read disturb for non-volatile storage

System for reducing read disturb for non-volatile storage

Method for programming non-volatile memory with self-adjusting maximum program loop

Retention margin program verification

Comprehensive erase verification for non-volatile memory

NAT SEMICONDUCTOR CORP

Self-regulating process-error trimmable PTAT current source

Clock generator circuit stabilized over temperature, process and power supply variations

Digitizing temperature measurement system and method of operation

RFID temperature logger incorporating a frequency ratio digitizing temperature sensor

Synchronized delta-VBE measurement system

Digitizing temperature measurement system

Method for synchronized delta-VBE measurement for calculating die temperature

Emitter area trim scheme for a PTAT current source

Charge balancing method in a current input ADC

Dual-channel instrumentation amplifier

Super-PTAT current source

Correlated double sampling modulation system with reduced latency of reference to input

Power-on reset circuit with low standby current and self-adaptive reset pulse width

Constant temperature coefficient self-regulating CMOS current source

Low noise correlated double sampling modulation system

Frequency ratio digitizing temperature sensor with linearity correction

SANDISK TECHNOLOGIES INC

Open block source bias adjustment for an incompletely programmed block of a nonvolatile storage device

On chip dynamic read level scan and error detection for nonvolatile storage

Detection of broken word-lines in memory arrays

Dynamically adjustable erase and program levels for non-volatile memory

Systems and methods for lower page writes

Verification process for non-volatile storage

WAN JUN

Data coding for improved ECC efficiency

Built in on-chip data scrambler for non-volatile memory

WESTERN DIGITAL TECH INC

Hybrid erase mode for high data retention in memory device

Command sequence for hybrid erase mode for high data retention in memory device

SANDISK TECHNOLOGIES LLC

First read countermeasures in memory

XIAOMI INC

Display screen or portion thereof with a graphical user interface

LEI BO

Erase and programming techniques to reduce the widening of state distributions in non-volatile memories

KHANDELWAL ANUBHAV

Reducing neighbor read disturb