Erase and programming techniques to reduce the widening of state distributions in non-volatile memories

Abstract

Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.

It is claimed: 
     
       1. A method of operating a non-volatile memory array comprising one or more erase blocks each having a plurality on memory cells formed along bitlines and wordlines, the method comprising:
 performing an erase operation on the memory cells of one or more selected erase blocks, the erase operation including:
 performing a stress phase, including:
 applying a pattern of voltage levels to the bitlines corresponding to the selected erase blocks, where the pattern includes a voltage differential between at least one pair of adjacent ones of the corresponding bit lines; and 
 while applying the pattern of voltage levels to the bitlines, applying a pulse of positive voltage to one or more of the wordlines corresponding to the selected erase blocks; and 
 
 performing an erase phase, including biasing the selected erase blocks to induce erasure of the memory cells thereof. 
 
 
     
     
       2. The method of  claim 1 , wherein the erase phase is performed after the stress phase in the erase operation. 
     
     
       3. The method of  claim 1 , wherein the stress phase is performed after the erase phase in the erase operation. 
     
     
       4. The method of  claim 1 , wherein said pulse is applied to all of the corresponding wordlines. 
     
     
       5. The method of  claim 1 , wherein the pattern of voltage levels includes applying a first positive voltage to a subset of one or more of the corresponding bitlines while the other ones of the corresponding bit lines are set at ground. 
     
     
       6. The method of  claim 5 , wherein the first positive voltage is the on-chip voltage supply level. 
     
     
       7. The method of  claim 5 , wherein the stress phase includes:
 applying a first pulse to all of the corresponding wordlines while applying the first positive level a first subset of the corresponding bitlines and ground to the others of the corresponding bitlines; and 
 applying a second pulse to all of the corresponding wordlines while applying the first positive level a second subset of the corresponding bitlines and ground to the others of the corresponding bitlines, where the first and second subsets differ. 
 
     
     
       8. The method of  claim 7 , wherein the first subset is ever alternate corresponding bitline and the second subset is those corresponding bitlines not in the first subset. 
     
     
       9. The method of  claim 7 , further comprising:
 between applying the first and second pulses, performing a gentle erase operation wherein the selected erase blocks are biased using a lower voltage differential applied to the memory cells of the selected erase blocks than in the erase phase. 
 
     
     
       10. The method of  claim 1 , wherein the array is of a NAND type of architecture where the memory cells are arranged as strings of a plurality of memory cells connected in series between first and second select gates and wherein the pulse is applied to all of wordlines of a string of memory cells selected for a stress operation. 
     
     
       11. The method of  claim 1 , further comprising:
 subsequent to perfuming the erase operation, performing a write operation on memory cells of the selected erase blocks. 
 
     
     
       12. The method of  claim 11 , further comprising:
 subsequent to performing the write operation, performing a subsequent erase operation on at least erase block of the selected erase blocks, wherein the subsequent erase operation applies a different pattern of voltage levels to the bitlines than the erase operation performed prior to the write operation. 
 
     
     
       13. The method of  claim 1 , wherein the characteristics of the pulse are altered varied upon the number of write-erase cycles that the selected erase blocks have previously endured. 
     
     
       14. The method of  claim 13 , wherein said characteristics include the amplitude of the pulse. 
     
     
       15. The method of  claim 1 , wherein the inclusion of the stress phase in the erase operation is determined based the number of write-erase cycles that the selected erase blocks have previously endured. 
     
     
       16. The method of  claim 15 , wherein the stress phase is included more frequently in the erase operation as the number of write-erase cycles increases. 
     
     
       17. A method of operating a non-volatile memory array of one or more erase blocks each having a plurality of memory cells formed along bitlines and wordlines, where the array is of a NAND type of architecture where a plurality of memory cells are connected in series between first and second select gates, the method comprising:
 performing an erase operation on the memory cells of one or more selected erase blocks, the erase operation including:
 performing a stress phase, including
 applying a first high voltage pulse to a first subset of one or more non-adjacent ones of the wordlines corresponding to the selected erase blocks, the first subset including at least one wordline corresponding to memory cells not adjacent to a select gate; and 
 while applying the high voltage pulse to the first subset of wordlines, setting the others of the wordlines corresponding to the selected erase blocks to a low voltage level; and 
 
 performing an erase phase, including biasing the selected erase blocks to induce erasure of the memory cells thereof. 
 
 
     
     
       18. The method of  claim 17 , wherein the low voltage level is sufficiently low so that the memory cells along the others of wordlines are non-conducting. 
     
     
       19. The method of  claim 17 , wherein the low voltage level is sufficiently high so that the memory cells along the others of wordlines are conducting. 
     
     
       20. The method of  claim 17 , wherein the low voltage level is set such that the memory cells along the others of wordlines are partially conducting. 
     
     
       21. The method of  claim 17 , wherein one or more of the bitlines corresponding to the selected erase blocks are set at ground. 
     
     
       22. The method of  claim 17 , wherein one or more of the bitlines corresponding to the selected erase blocks are set at program inhibit voltage. 
     
     
       23. The method of  claim 17 , further comprising applying a voltage to control gates of select gates corresponding to the selected erase blocks so that they are in a conducting state. 
     
     
       24. The method of  claim 17 , wherein the erase phase is performed after the stress phase in the erase operation. 
     
     
       25. The method of  claim 17 , wherein the stress phase is performed after the erase phase in the erase operation. 
     
     
       26. The method of  claim 17 , wherein the stress phase further includes:
 after applying the first high voltage pulse to the first subset, applying a second high voltage pulse to a second subset of one or more non-adjacent ones of the wordlines corresponding to the selected erase blocks, where the first and second subsets differ; and 
 while applying the second high voltage pulse to the second subset of wordlines, setting the others of the wordlines not in the second subset to a low voltage level. 
 
     
     
       27. The method of  claim 26 , wherein the first subset is ever alternate corresponding wordline and the second subset is those corresponding wordlines not in the first subset. 
     
     
       28. The method of  claim 26 , further comprising:
 between applying the first and second high voltage pulses, performing a gentle erase operation wherein the selected erase blocks are biased using a lower voltage differential applied to the memory cells of the selected erase blocks than in the erase phase. 
 
     
     
       29. The method of  claim 17 , further comprising:
 subsequent to perfuming the erase operation, performing a write operation on memory cells of the selected erase blocks. 
 
     
     
       30. The method of  claim 29 , further comprising:
 subsequent to performing the write operation, performing a subsequent erase operation on at least erase block of the selected erase blocks, wherein the subsequent erase operation uses a different first subset than the erase operation performed prior to the write operation. 
 
     
     
       31. The method of  claim 17 , wherein the characteristics of the high voltage pulse are altered varied upon the number of write-erase cycles that the selected erase blocks have previously endured. 
     
     
       32. The method of  claim 31 , wherein said characteristics include the amplitude of the high voltage pulse. 
     
     
       33. The method of  claim 17 , wherein the inclusion of the stress phase in the erase operation is determined based the number of write-erase cycles that the selected erase blocks have previously endured. 
     
     
       34. The method of  claim 33 , wherein the stress phase is included more frequently in the erase operation as the number of write-erase cycles increases. 
     
     
       35. A method of writing data to a non-volatile memory, comprising:
 performing an alternating series of program and verify phases on a selected plurality of memory cells formed along a selected wordline, 
 wherein the verify phase includes performing a verify operation that individually locks out from further programming selected memory cells in response to successfully verifying as programmed to a corresponding target state, and 
 wherein the programming phase includes applying a first and a second programming pulse to the selected wordline without an intervening verify operation, wherein a non-selected wordline adjacent to the selected wordline is set to a first voltage during the first programming pulse and to a second voltage during the second voltage during the second programming pulse, wherein the first and second voltages are distinct positive voltages. 
 
     
     
       36. The method of  claim 35 , wherein the first voltage is lower than the second voltage. 
     
     
       37. The method of  claim 35 , wherein the non-volatile memory is of a NAND-type architecture. 
     
     
       38. The method of  claim 37 , wherein for a selected wordline that is not an edge wordline of the NAND structure, both non-selected wordlines adjacent to the selected wordline are set to the first voltage during the first programming pulse and to the second voltage during the second voltage during the second programming pulse. 
     
     
       39. The method of  claim 37 , wherein the first voltage is lower than the second voltage, and wherein non-adjacent non-selected wordlines of the NAND structure are set to the second voltage during the first and second programming pulses. 
     
     
       40. The method of  claim 35 , wherein the first and second programming pulses of each programming phase are of the same amplitude.