Inventor

KHANDELWAL ANUBHAV

US38 patents

⚠️ This page may combine multiple inventors who share the name “KHANDELWAL ANUBHAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KHANDELWAL ANUBHAV

SANDISK TECHNOLOGIES LLC

Reducing post-read disturb in a nonvolatile memory device

Techniques for reducing read disturb in partially written blocks of non-volatile memory

Read verify for improved soft bit information for non-volatile memories with residual resistance

Memory programming with selectively skipped bitscans and fewer verify pulses for performance improvement

Apparatus and method for detecting neighbor plane erase failures

Control gate signal for data retention in nonvolatile memory

Control gate signal for data retention in nonvolatile memory

Memory apparatus and method of operation using periodic normal erase dummy cycle to improve stripe erase endurance and data retention

Programming techniques for memory devices having partial drain-side select gates

“Read after erase” method for catching single word line “slow to erase” signature in nonvolatile memory structures

Programming techniques with fewer verify pulses to improve performance

Systems and methods for high-performance write operations

Non-volatile memory with methods to reduce creep-up field between dummy control gate and select gate

System and methods for programming nonvolatile memory having partial select gate drains

Application based verify level offsets for non-volatile memory

Countermeasures for periodic over programming for non-volatile memory

Systems and methods for high-performance write operations

Non-volatile memory with faster post-erase defect testing

Vera detection method to catch erase fail

SANDISK TECHNOLOGIES INC

Ramping pass voltage to enhance channel boost in memory device

Methods and systems that selectively inhibit and enable programming of non-volatile storage elements

Real time ramp rate adjustment for better performance and current consumption tradeoff

Memory apparatus and method of operation using dynamic max program loop

Enhanced bit error rate estimation scan process

Program pulse duration increase for NAND program failure

WESTERN DIGITAL TECH INC

Reducing post-read disturb in a nonvolatile memory device

System handling for first read read disturb

Adaptive erase fail bit criteria

Boundary word line voltage shift

Optimized erratic program detection process

System and method for string-based erase verify to create partial good blocks

SANDISK CORP

Two pass erase for non-volatile storage

LEI BO

Erase and programming techniques to reduce the widening of state distributions in non-volatile memories

KHANDELWAL ANUBHAV

Reducing neighbor read disturb

HEMINK GERRIT JAN

Ramping pass voltage to enhance channel boost in memory device, with optional temperature compensation

MOKHLESI NIMA

Two pass erase for non-volatile storage

LI YAN

Programming memory with bit line floating to reduce channel-to-floating gate coupling

KOCHAR MRINAL

Enhanced dynamic read process with single-level cell segmentation