Inventor

CHOI DAESIK

KR81 patents

⚠️ This page may combine multiple inventors who share the name “CHOI DAESIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOI DAESIK

CHOI DAESIK

Semiconductor package system with through silicon via interposer

Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV

Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material

Integrated circuit packaging system with conductive pillars and method of manufacture thereof

Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias

Integrated circuit packaging system with vertical interconnection and method of manufacture thereof

Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties

Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillar

Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate

Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias

Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structures

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

Semiconductor device and method of forming leadframe with conductive bodies for vertical electrical interconnect of semiconductor die

Semiconductor device and method of forming thermal interface material and heat spreader over semiconductor die

Integrated circuit packaging system with heat slug and method of manufacture thereof

Integrated circuit packaging system with heat conduction and method of manufacture thereof

Semiconductor device and method of controlling warpage in semiconductor package

STATS CHIPPAC LTD

Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate

Integrated circuit packaging system with conductive pillars and method of manufacture thereof

Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material

Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties

Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV

Semiconductor device with protective layer over exposed surfaces of semiconductor die

Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties

Semiconductor device including bump formed on substrate to prevent extremely-low dielectric constant (ELK) interlayer dielectric layer (ILD) delamination during reflow process

Semiconductor method of forming bump on substrate to prevent ELK ILD delamination during reflow process

Integrated circuit package system employing an offset stacked configuration

Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate

KIM OHHAN

Semiconductor device and method of forming WLCSP structure using protruded MLP

Semiconductor device and method of forming WLCSP structure using protruded MLP

Semiconductor device and method of forming a low profile dual-purpose shield and heat-dissipation structure

CHO SUNGWON

Semiconductor device and method of forming electrical interconnection between semiconductor die and substrate with continuous body of solder tape

Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump

Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die

KIM MINJUNG

Integrated circuit packaging system with coupling features and method of manufacture thereof

Integrated circuit packaging system with warpage preventing mechanism and method of manufacture thereof

KOREA ELECTRONICS TELECOMM

N grouping of traffic and pattern-free internet worm response system and method using N grouping of traffic

YOON HEE SOO

Battery module of improved safety and middle or large-sized battery pack containing the same

STS SC & TELECOMM CO LTD

Integrated circuit package and method for manufacturing the same

PAGAILA REZA A

Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die

LEE SANG-HO

Integrated circuit package system for stackable devices

YANG DEOKKYUNG

Integrated circuit packaging system with stackable package and method of manufacture thereof

HA JONG-WOO

Integrated circuit packaging system with stacked configuration and method of manufacture thereof

PARK SOO-SAN

Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereof

BAE JOHYUN

Integrated circuit packaging system with stack device

KIM OH HAN

Integrated circuit packaging system with underfill and method of manufacture thereof

PARK YISU

Integrated circuit packaging system having warpage prevention structures

LEE KYUNGHOON

Semiconductor device and method of depositing underfill material with uniform flow rate

STATS CHIPPAC PTE LTD

Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package

CHOI JOONYOUNG

Integrated circuit packaging system with interconnects and method of manufacture thereof