Inventor
LIN HSIEN-CHIN
TW30 patents
⚠️ This page may combine multiple inventors who share the name “LIN HSIEN-CHIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
13 patentsUS10319581B1Jun 11, 2019
Cut metal gate process for reducing transistor spacing
TAIWAN SEMICONDUCTOR MFG CO LTD14 citations94
US10978351B2Apr 13, 2021
Etch stop layer between substrate and isolation structure
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations73
US10224245B2Mar 5, 2019
Method of making a finFET, and finFET formed by the method
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US9659776B2May 23, 2017
Doping for FinFET
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations72
US12374542B2Jul 29, 2025
Cut metal gate process for reducing transistor spacing
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11948842B2Apr 2, 2024
Etch stop layer between substrate and isolation structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11721544B2Aug 8, 2023
Cut metal gate process for reducing transistor spacing
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11239072B2Feb 1, 2022
Cut metal gate process for reducing transistor spacing
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US10991628B2Apr 27, 2021
Etch stop layer between substrate and isolation structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US10868003B2Dec 15, 2020
Creating devices with multiple threshold voltages by cut-metal-gate process
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations61
US10461078B2Oct 29, 2019
Creating devices with multiple threshold voltage by cut-metal-gate process
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations61
US10651030B2May 12, 2020
Cut metal gate process for reducing transistor spacing
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US10515856B2Dec 24, 2019
Method of making a FinFET, and FinFET formed by the method
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations47
TAIWAN SEMICONDUCTOR MFG
10 patentsUS6444544B1Sep 3, 2002
Method of forming an aluminum protection guard structure for a copper metal structure
TAIWAN SEMICONDUCTOR MFG76 citations96
US6362035B1Mar 26, 2002
Channel stop ion implantation method for CMOS integrated circuits
TAIWAN SEMICONDUCTOR MFG26 citations93
US6380021B1Apr 30, 2002
Ultra-shallow junction formation by novel process sequence for PMOSFET
TAIWAN SEMICONDUCTOR MFG49 citations92
US6235600B1May 22, 2001
Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a teos liner deposition
TAIWAN SEMICONDUCTOR MFG29 citations92
US9373704B2Jun 21, 2016
Multiple-gate semiconductor device and method
TAIWAN SEMICONDUCTOR MFG6 citations84
US8895383B2Nov 25, 2014
Multiple-gate semiconductor device and method
TAIWAN SEMICONDUCTOR MFG7 citations84
US9362404B2Jun 7, 2016
Doping for FinFET
TAIWAN SEMICONDUCTOR MFG8 citations83
US8994116B2Mar 31, 2015
Hybrid gate process for fabricating FinFET device
TAIWAN SEMICONDUCTOR MFG10 citations82
US8034677B2Oct 11, 2011
Integrated method for forming high-k metal gate FinFET devices
TAIWAN SEMICONDUCTOR MFG9 citations82
USRE40138EMar 4, 2008
Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a Teos liner deposition
TAIWAN SEMICONDUCTOR MFG1 citations52