Inventor

UTOMO HENRY K

US62 patents

⚠️ This page may combine multiple inventors who share the name “UTOMO HENRY K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

UTOMO HENRY K

IBM

Chemical treatment to retard diffusion in a semiconductor overlayer

Structure and method for making strained channel field effect transistor using sacrificial spacer

Strained finFET with an electrically isolated channel

Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer

In situ doped embedded sige extension and source/drain for enhanced PFET performance

Forming self-aligned contacts on pillar structures

Fin field effect transistors having heteroepitaxial channels

Strained finFET with an electrically isolated channel

FinFET having suppressed leakage current

Self-aligned contact employing a dielectric metal oxide spacer

Structure and method to form multilayer embedded stressors

Structure and method to form multilayer embedded stressors

Methods for forming CMOS devices with intrinsically stressed metal silicide layers

Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer

Semiconductor manufactured nano-structures for microbe or virus trapping or destruction

Structure and method for making strained channel field effect transistor using sacrificial spacer

Hybrid orientation substrate and method for fabrication of thereof

Contact via structures

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Embedded source/drain structure for tall finFET and method of formation

finFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Silicon-germanium fins and silicon fins on a bulk substrate

Semiconductor manufactured nano-structures for microbe or virus trapping or destruction

Semiconductor manufactured nano-structures for microbe or virus trapping or destruction

Contact via structures

Semiconductor fin isolation by a well trapping fin portion

Semiconductor manufactured nano-structures for microbe or virus trapping or destruction

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Semiconductor manufactured nano-structures for microbe or virus trapping or destruction

Embedded source/drain structure for tall FinFet and method of formation

Embedded source/drain structure for tall FinFET and method of formation

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Forming self-aligned contacts on pillar structures

GLOBALFOUNDRIES INC

Junction butting structure using nonuniform trench shape

FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

Forming fins of different semiconductor materials on the same substrate

Conformal buffer layer in source and drain regions of fin-type transistors

Asymmetric semiconductor device and method of forming same

Diamond shaped source drain epitaxy with underlying buffer layer

Fin-type field-effect transistors with strained channels

Methods of forming uniform and pitch independent fin recess

UTOMO HENRY K

Method of forming source and drain of field-effect-transistor and structure thereof

Method of forming E-fuse in replacement metal gate manufacturing process

Planar silicide semiconductor structure

Structure and method for replacement metal gate field effect transistors

LI YING

Self-aligned contact employing a dielectric metal oxide spacer

YANG JONG HO

Methods of forming p-channel field effect transistors having SiGe source/drain regions

ST MICROELECTRONICS INC

Prevention of faceting in epitaxial source drain transistors

SHANG HUILING

Method of forming a shallow trench isolation embedded polysilicon resistor