Inventor
MATICK RICHARD E
US19 patents
Patents
19 patentsUS4577293AMar 18, 1986
Distributed, on-chip cache
IBM145 citations97
US4649516AMar 10, 1987
Dynamic row buffer circuit for DRAM
IBM76 citations95
US4541075ASep 10, 1985
Random access memory having a second input/output port
IBM79 citations95
US4667305AMay 19, 1987
Circuits for accessing a variable width data bus with a variable width data field
IBM132 citations94
US4905188AFeb 27, 1990
Functional cache memory chip architecture for improved cache access
IBM85 citations93
US7499312B2Mar 3, 2009
Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line
IBM25 citations92
US6981096B1Dec 27, 2005
Mapping and logic for combining L1 and L2 directories and/or arrays
IBM21 citations92
US5388072AFeb 7, 1995
Bit line switch array for electronic computer memory
IBM32 citations92
US4589092AMay 13, 1986
Data buffer having separate lock bit storage array
IBM38 citations92
US4616310AOct 7, 1986
Communicating random access memory
IBM37 citations91
US4287575ASep 1, 1981
High speed high density, multi-port random access memory cell
IBM30 citations91
US7289369B2Oct 30, 2007
DRAM hierarchical data path
IBM12 citations84
US4663729AMay 5, 1987
Display architecture having variable data width
IBM22 citations81
US7821858B2Oct 26, 2010
eDRAM hierarchical differential sense AMP
IBM7 citations74
US7471546B2Dec 30, 2008
Hierarchical six-transistor SRAM
IBM7 citations74
US7460387B2Dec 2, 2008
eDRAM hierarchical differential sense amp
IBM8 citations74
US7460423B2Dec 2, 2008
Hierarchical 2T-DRAM with self-timed sensing
IBM2 citations63
US7709299B2May 4, 2010
Hierarchical 2T-DRAM with self-timed sensing
IBM1 citations52
US5890215AMar 30, 1999
Electronic computer memory system having multiple width, high speed communication buffer
IBM0 citations41