Inventor

HUNG SHUO-NAN

TW56 patents

⚠️ This page may combine multiple inventors who share the name “HUNG SHUO-NAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUNG SHUO-NAN

MACRONIX INT CO LTD

Page buffer structure and fast continuous read

Storage scheme for built-in ECC operations

Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks

Method and device for reducing coupling noise during read operation

NAND flash biasing operation

Method for erasing a flash EEPROM

Output buffer drive circuit with initial drive for semiconductor devices

On chip block repair scheme

Non-sequential page continuous read

Fast page continuous read

3D memory array with read bit line shielding

Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks

Memory repair redundancy with array cache redundancy

Word line driver circuit for selecting and deselecting word lines

Data retention in memory devices

Bit error rate reduction technology

System for sharing status among multiple devices

Universal data path architecture for different data array

Continuous read with multiple read commands

Non-sequential page continuous read

Flash memory system and flash memory device thereof

Continuous read with multiple read commands

In-place refresh operation in flash memory

Page buffer counting for in-memory search

Data retention in memory devices

Memory system having planes with multibit status

Managing data refresh in semiconductor devices

In memory data computation and analysis

Memory supporting multiple types of operations

Method to support high reliability multiple times program non-volatile configuration setting

Memory device, electronic device, and associated read method

Circuit and method for adjusting select gate voltage of non-volatile memory during erasure of memory cells based on a well voltage

Circuit for adjusting a select gate voltage of a non-volatile memory during erasure of memory cells based on a well voltage

Memory access method and flash memory using the same

Temperature compensation circuit and method for sensing memory

Method for an integrated circuit memory with a status memory for storing repair statuses of row blocks of main column blocks

Program method, data recovery method, and flash memory using the same

Method and apparatus for indicating bad memory areas

Management of non-volatile memory

Method and apparatus for reducing read disturb in memory

HUNG CHUN-HSIUNG

Architecture for a 3D memory array

Method and apparatus for reducing read disturb in memory

On-the-fly repair method for memory

Method and apparatus for reducing read disturb in memory

HUNG SHUO-NAN

3D memory array with read bit line shielding

Method and apparatus for copying data with a memory array having redundant memory

Decoder for NAND memory

Method and apparatus for indicating bad memory areas

CHEN CHUNG-KUANG

Memory access method and flash memory using the same

HO WEN-CHIAO

Memory device and operation method thereof