Inventor

FRANK MARTIN M

US105 patents

⚠️ This page may combine multiple inventors who share the name “FRANK MARTIN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FRANK MARTIN M

IBM

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

Ferroelectric gate dielectric with scaled interfacial layer for steep sub-threshold slope field-effect transistor

High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

Semiconductor device having dual metal gates and method of manufacture

Techniques for enabling multiple Vt devices using high-K metal gate stacks

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide

Scavenging metal stack for a high-k gate dielectric

Suspended germanium photodetector for silicon waveguide

Low threshold voltage semiconductor device with dual threshold voltage control means

Hafnium oxide and zirconium oxide based ferroelectric devices with textured iridium bottom electrodes

BEOL cross-bar array ferroelectric synapse units for domain wall movement

Patterned gate dielectrics for III-V-based CMOS circuits

Method of lateral oxidation of NFET and PFET high-K gate stacks

Fabrication of low threshold voltage and inversion oxide thickness scaling for a high-k metal gate p-type MOSFET

Gate electrode optimized for low voltage operation

Scavanging metal stack for a high-k gate dielectric

Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow

Low threshold voltage semiconductor device with dual threshold voltage control means

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics

Method of forming gate stack for semiconductor electronic device

Method of forming a semiconductor structure using a non-oxygen chalcogen passivation treatment

Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow

Semiconductor devices containing an epitaxial perovskite/doped strontium titanate structure

Multi-terminal cross-point synaptic device using nanocrystal dot structures

Voltage controlled highly linear resistive elements

Fast recrystallization of hafnium or zirconium based oxides in insulator-metal structures

Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end

Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap

Ferroelectric gate dielectric with scaled interfacial layer for steep sub-threshold slope field-effect transistor

Disposable laser/flash anneal absorber for embedded neuromorphic memory device fabrication

Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end

Stressed nanowire stack for field effect transistor

Domain wall control in ferroelectric devices

Domain wall control in ferroelectric devices

Patterned gate dielectrics for III-V-based CMOS circuits

High-K gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material

Hydroxyl group termination for nucleation of a dielectric metallic oxide

Gate electrode with stabilized metal semiconductor alloy-semiconductor stack

Gate electrode optimized for low voltage operation

FRANK MARTIN M

Techniques for enabling multiple Vt devices using high-K metal gate stacks

Controlling threshold voltage in carbon based field effect transistors

Techniques for enabling multiple Vt devices using high-K metal gate stacks

ASSEFA SOLOMON

Suspended germanium photodetector for silicon waveguide

BOJARCZUK JR NESTOR A

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

ANDO TAKASHI

Structure and method to form input/output devices

DUBOURDIEU CATHERINE A

Ferroelectric semiconductor transistor devices having gate modulated conductive layer

GLOBALFOUNDRIES INC

Changing effective work function using ion implantation during dual work function metal gate integration