Inventor
WIEDMANN SIEGFRIED K
30 patents
Patents
30 patentsUS4785341ANov 15, 1988
Interconnection of opposite conductivity type semiconductor regions
IBM34 citations92
US4694433ASep 15, 1987
Semiconductor memory having subarrays and partial word lines
IBM25 citations92
US4338622AJul 6, 1982
Self-aligned semiconductor circuits and process therefor
IBM24 citations80
US4254428AMar 3, 1981
Self-aligned Schottky diode structure and method of fabrication
IBM25 citations78
US3955210AMay 4, 1976
Elimination of SCR structure
IBM29 citations76
US4596000AJun 17, 1986
Semiconductor memory
IBM10 citations74
US4425574AJan 10, 1984
Buried injector memory cell formed from vertical complementary bipolar transistor circuits and method of fabrication therefor
IBM16 citations74
US4306159ADec 15, 1981
Bipolar inverter and NAND logic circuit with extremely low DC standby power
IBM8 citations74
US4274891AJun 23, 1981
Method of fabricating buried injector memory cell formed from vertical complementary bipolar transistor circuits utilizing mono-poly deposition
IBM15 citations74
US4158237AJun 12, 1979
Monolithically integrated storage cells
IBM15 citations74
US4521873AJun 4, 1985
Method of and circuit arrangement for reading an integrated semiconductor store with storage cells in MTL (I2 L) technology
IBM15 citations73
US4280198AJul 21, 1981
Method and circuit arrangement for controlling an integrated semiconductor memory
IBM9 citations73
US4023148AMay 10, 1977
Write speed-up circuit for integrated data memories
IBM14 citations73
US4412312AOct 25, 1983
Multiaddressable highly integrated semiconductor storage
IBM7 citations72
US4035664AJul 12, 1977
Current hogging injection logic
IBM16 citations72
US4027176AMay 31, 1977
Sense circuit for memory storage system
IBM18 citations72
US4007451AFeb 8, 1977
Method and circuit arrangement for operating a highly integrated monolithic information store
IBM11 citations72
US3956641AMay 11, 1976
Complementary transistor circuit for carrying out boolean functions
IBM10 citations72
US5467311ANov 14, 1995
Circuit for increasing data-valid time which incorporates a parallel latch
IBM9 citations69
US4992981AFeb 12, 1991
Double-ended memory cell array using interleaved bit lines and method of fabrication therefore
IBM9 citations68
US4458162AJul 3, 1984
TTL Logic gate
IBM6 citations63
US4319344AMar 9, 1982
Method and circuit arrangement for discharging bit line capacitances of an integrated semiconductor memory
IBM4 citations62
US4313177AJan 26, 1982
Storage cell simulation for generating a reference voltage for semiconductor stores in mtl technology
IBM3 citations62
US4259730AMar 31, 1981
IIL With partially spaced collars
IBM2 citations62
US4346458AAug 24, 1982
I2 L Monolithically integrated storage arrangement
IBM6 citations61
US5121357AJun 9, 1992
Static random access split-emitter memory cell selection arrangement using bit line precharge
IBM3 citations58
US4626710ADec 2, 1986
Low power logic circuit with storage charge control for fast switching
IBM1 citations52
US4535425AAug 13, 1985
Highly integrated, high-speed memory with bipolar transistors
IBM1 citations52
US4713814ADec 15, 1987
Stability testing of semiconductor memories
IBM4 citations51
US4334294AJun 8, 1982
Restore circuit for a semiconductor storage
IBM0 citations41