Restore circuit for a semiconductor storage

Abstract

Disclosed is a restore circuit for restoring an integrated semiconductor storage array having storage cells consisting of bipolar transistors. The restore circuit includes a reference voltage generator, an impedance converter, and switches to connect the reference voltage generator and the impedance converter to the storage array. The reference voltage generating circuit includes a current source and at least one reference storage cell identical in construction to the storage cells of the array. The reference voltage generating circuit provides a reference voltage to the impedance converter which supplies a second reference voltage to the array at a greatly reduced impedance. The equivalent circuit of the storage cells is that of a capacitor in parallel with a diode. Thus, the impedance converter provides an initial surge of capacitive current which restores the cells, followed by a standby current which is a function of the diode characteristics of the cell equivalent circuit.

We claim: 
     
       1. A circuit for restoring an integrated semiconductor storage array having storage cells consisting of bipolar transistors (and PNP load devices) at cross-points of word lines and bit line pairs comprising: a reference voltage generator circuit including a current source connected to at least one reference storage cell and providing a first reference voltage;   impedance converting means connected to said reference voltage generating circuit and receiving as an output said first reference voltage and providing a second reference voltage at a low impedance output;   first switch means connecting said second reference voltage, by means of said bit line pairs to the PNP load devices of the array storage cells;   second switch means for connecting a third reference voltage, by means of said word lines, to the array storage cell load devices, said third reference potential also being connected to the at least one reference storage cell in the reference voltage generating circuit.   
     
     
       2. A circuit as in claim 1 wherein said impedance converting means comprises: first, second, and third transistors each having base, emitter, and collector regions, the emitters of the first and second transistors being connected in common and to another current source, the collector of the second transistor being connected to the base of the third transistor, the base of the second transistor being connected to the emitter of the third transistor, the collector regions of the first and third transistors being connected in common and to a voltage source, the base of the first transistor receiving the first reference voltage from the reference voltage generating circuit, the emitter of the third transistor providing the second reference voltage as an output of the impedance converter; and   unidirectionally conducting means connected to the base of the third transistor with a control terminal attached to the unidirectionally conducting means controlling the on and off state of said third transistor.