Inventor

HOLTEY THOMAS O

US44 patents

⚠️ This page may combine multiple inventors who share the name “HOLTEY THOMAS O”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOLTEY THOMAS O

HONEYWELL INF SYSTEMS

I/O Request interrupt mechanism

Private cache-to-CPU interface in a bus oriented data processing system

Multi-configurable cache store system

High speed buffer memory system with word prefetch

Computer display system for producing color text and graphics

Multiple color generation on a display

Microprocessor controlled communications controller having a stretched clock cycle

Data processing system having direct memory access bus cycle

Continuous updating of cache store

Data multiplex control facility

Communications subsystem having a direct connect clock

Hardware for extending microprocessor addressing capability

Computer system having a paging apparatus for mapping virtual addresses to real addresses for a memory of a multiline communications controller

I/O Priority resolver

Multi-way vectored interrupt capability

Speeding up the response time of the direct multiplex control transfer facility

Multiple beam high definition page display

Multiple beam high definition page display

Communication subsystem with an automatic abort transmission upon transmit underrun

Data processing system having apparatus in a communications subsystem for establishing byte synchronization

Communications subsystem having a self-latching data monitor and storage device

Communications subsystem idle link state detector

Word oriented high speed buffer memory system connected to a system bus

Apparatus for verifying the integrity of information stored in a data processing system memory

Variable loadable character generator

Digital serial interface with encode logic for transmission

Hardware in a computer system for maintenance by a remote computer system

Apparatus and method for testing and verifying the refresh logic of dynamic MOS memories

Apparatus and method for testing and verifying the timing logic of a cathode ray tube display

Diskette subsystem fault isolation via video subsystem loopback

Firmware simulation of diskette data via a video signal

Digital decode logic for converting successive binary zero pulses having opposite polarity to a stream of data pulses

BULL HN INFORMATION SYST

Secure application card for sharing application data and procedures among a plurality of microprocessors

Secure memory card

Communications controller interface

Firmware state apparatus for controlling sequencing of processing including test operation in multiple data lines of communication

Dual microprocessor control system

HONEYWELL BULL

Facility for passing data used by one operating system to a replacement operating system

Pattern generation for a graphics display

Microcomputer system with independent operating systems

BULL NH INFORMATION SYSTEMS IN

Secure memory card with programmed controlled security access control

NORTEL NETWORKS LTD

Feedback output queuing system, apparatus, and method

EAGLEVIEW INC

Computer-assisted system for interactively brokering goods or services between buyers and sellers

AVAYA INC

Method and apparatus for selectively reading counter information in a network device