Inventor

CALDWELL ANDREW

US106 patents

⚠️ This page may combine multiple inventors who share the name “CALDWELL ANDREW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CALDWELL ANDREW

CADENCE DESIGN SYSTEMS INC

Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction

Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits

Method and apparatus for producing multi-layer topological routes

Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs

Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits

Method and apparatus for computing cost of a path expansion to a surface

Method and apparatus for decomposing a design layout

Method and apparatus for routing a set of nets

Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC&#39;s

Method and apparatus for decomposing a region of an integrated circuit layout

Method and apparatus for identifying a path between source and target states

IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout

Gridless IC layout and method and apparatus for generating such a layout

Method and apparatus for routing nets in an integrated circuit layout

Method and apparatus for defining vias

Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiring

Method and apparatus for routing

Method and apparatus for propagating a function

Method and apparatus for routing a set of nets

Polygonal vias

Method and apparatus for generating multi-layer routes

Method and apparatus for routing with independent goals on different layers

Routing method and apparatus

Method and apparatus for routing

Interconnect lines with non-rectilinear terminations

Method and apparatus for identifying optimized via locations

Method and apparatus for routing groups of paths

Method and apparatus for identifying a path between source and target states in a space with more than two dimensions

Method and apparatus for routing

TABULA INC

Method and apparatus for decomposing functions in a configurable IC

Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources

Operational time extension

Operational time extension

Method and apparatus for function decomposition

Configurable integrated circuit with a 4-to-1 multiplexer

Configurable ICs that conditionally transition through configuration data sets

IC that efficiently replicates a function to save logic and routing resources

System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture

CALDWELL ANDREW

Sequential delay analysis by placement engines

Decision modules

Decision modules in integrated circuit design

ROHE ANDRE

Operational time extension

Operational time extension

HUTCHINGS BRAD

Translating a user design in a configurable IC for debugging the user design

Translating a user design in a configurable IC for debugging the user design

FRANKLE JONATHAN

Method and apparatus for routing with independent goals on different layers

VOOGEL MARTIN

Configurable storage elements

ALTERA CORP

Sequential timing using level-sensitive clocked elements to optimize IC performance

TEIG STEVEN

Timing operations in an IC with configurable circuits

REDGRAVE JASON

Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC

Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's