System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture

Abstract

Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

1. A method of presenting digital memory to a user design of an integrated circuit (IC) comprising configurable circuits, the method comprising:
 reading a multi-bit word from a digital memory of the IC; 
 passing said multi-bit word through a barrel shifter in order to create a plurality of shifted multi-bit memory words at output circuits of the barrel shifter; 
 at a subset of the output circuits of the barrel shifter, selecting a narrower word that is a subset of the bits of a particular shifted multi-bit word from the plurality of shifted multi-bit words, said narrower word having fewer bits than the particular shifted multi-bit word; and 
 passing the narrower word from the subset of the output circuits without passing the other bits of the particular shifted multi-bit word. 
 
   
   
     2. The method of  claim 1  wherein passing said narrower word comprises passing said narrower word to other configurable circuits implementing said user design. 
   
   
     3. The method of  claim 1 , wherein said narrower word includes the least significant bit of said shifted multi-bit word. 
   
   
     4. The method of  claim 1 , wherein said narrower word includes the most significant bit of said shifted multi-bit word. 
   
   
     5. The method of  claim 1 , wherein said barrel shifter comprises non-neighboring offset connections and connections between two groups of configurable circuits in a particular row or column of groups of circuits. 
   
   
     6. The method of  claim 1  further comprising receiving memory address bits. 
   
   
     7. The method of  claim 6 , wherein said memory address bits comprise a set of bits for identifying a memory location of said digital memory. 
   
   
     8. The method of  claim 7 , wherein said memory address bits comprise a set of bits for determining a number of bits to shift said multi-bit word. 
   
   
     9. The method of  claim 1 , wherein said barrel shifter comprises at least one multiplexer. 
   
   
     10. The method of  claim 1 , wherein said barrel shifter comprises at least one look up table. 
   
   
     11. A method of accessing a wide and shallow physical memory in an integrated circuit (IC) as a narrow and deep logical memory, wherein the logical memory has more words than the physical memory by a particular factor, the method comprising:
 receiving a memory address that identifies a location in the logical memory, said memory address comprising a set of real memory address bits and a set of logical memory position bits; 
 retrieving an original memory word from a physical memory using said set of real memory address bits; 
 shifting said original memory word by an amount determined by said logical memory position bits by using a barrel shifter in order to create a shifted memory word; and 
 reading a part of said shifted memory word, wherein the part has a number of bits determined by the number of bits in the shifted memory word divided by the particular factor. 
 
   
   
     12. The method of  claim 11 , wherein the particular factor is two to the power of the number of logical memory bits. 
   
   
     13. The method of  claim 11 , wherein said logical memory position bits represent a binary number. 
   
   
     14. The method of  claim 13 , wherein said shifting is by a number of bits equal to the number of bits in the shifted memory word divided by the particular factor times said binary number. 
   
   
     15. The method of  claim 11 , wherein said barrel shifter is implemented with configurable circuits of the IC. 
   
   
     16. The method of  claim 15 , wherein said barrel shifter comprises non-neighboring offset connectors. 
   
   
     17. The method of  claim 16 , wherein said barrel shifter is implemented using connectors that connect two tiles within the same row or column. 
   
   
     18. An integrated circuit (IC) comprising:
 a) a digital memory; 
 b) a first set of circuits for supplying a first set of memory address bits to the digital memory, wherein said first set of memory address bits identifies a location of a data word in the digital memory; 
 c) a barrel shifter for shifting a copy of said data word, said barrel shifter comprising a plurality of outputs; 
 d) a second set of circuits for determining a number of bits to shift said copy of the data word to generate a shifted multi-bit word, wherein the number of bits to shift is based on a second set of memory address bits, wherein the second set of memory address bits determines which of a plurality of subsets of the shifted multi-bit word is received at a particular group of circuits and determines which other subsets of the shifted multi-bit word are not received from the barrel shifter; and 
 e) the particular group of circuits, wherein the particular group of circuits is for receiving narrow data words with fewer bits than the shifted multi-bit word, each narrow data word comprising at least two bits, wherein the narrow data words are subsets of the data word and the data word comprises a larger number of bits than each of the narrow data words. 
 
   
   
     19. The IC of  claim 18 , wherein said barrel shifter comprises non-neighboring offset connectors. 
   
   
     20. An integrated circuit (IC) comprising:
 a) a physical memory for storing data words of a first width, said physical memory accessible through a memory address that 
 comprises (i) a first identifier of a particular memory location that contains a particular data word of the first width in the physical memory and (ii) a second identifier of a memory location of a data word of a second width within said particular data word of a first width, wherein the second width is narrower than the first width; and 
 b) a barrel shifter for (i) shifting said particular data word of the first width by an amount determined by the second identifier in order to create a shifted multi-bit word of the first width, (ii) presenting, as a data word of the second width, the bits of the shifted multi-bit word that represent the received memory address to a group of circuits, wherein the group of circuits is for receiving any one of a plurality of data words of the second width, based on a size of the shift, and (iii) discarding the bits of the shifted multi-bit word that do not represent a received memory address location. 
 
   
   
     21. The IC of  claim 20 , wherein the number of bits in the second identifier is dependent on the ratio of the first width to the second width. 
   
   
     22. The IC of  claim 20 , wherein the number of bits in the second identifier is the log base two of the ratio of the first width to the second width.