Inventor · disambiguated record
Andrew Caldwell
Also filed as: CALDWELL ANDREW · CALDWELL ANDREW H
97 granted patents·7 pending applications·1,586 citations·filing 1975–2015
99Inventor score
Top patents by PatentIndex Score
104 records- 0198US7898291B2Operational time extensionTABULA INC·Filed 2009·Granted Mar 1, 2011·36 cites·19 claims
- 0298US7587698B1Operational time extensionTABULA INC·Filed 2007·Granted Sep 8, 2009·50 cites·8 claims
- 0398US7530033B2Method and apparatus for decomposing functions in a configurable ICTABULA INC·Filed 2005·Granted May 5, 2009·61 cites·17 claims
- 0498US7236009B1Operational time extensionROHE ANDRE·Filed 2005·Granted Jun 26, 2007·67 cites·18 claims
- 0597US7372297B1Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resourcesTABULA INC·Filed 2005·Granted May 13, 2008·59 cites·21 claims
- 0696US6711727B1Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Mar 23, 2004·91 cites·20 claims
- 0796US6526555B1Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compactionCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Feb 25, 2003·104 cites·20 claims
- 0895US7535252B1Configurable ICs that conditionally transition through configuration data setsTABULA INC·Filed 2007·Granted May 19, 2009·31 cites·18 claims
- 0994US7610566B1Method and apparatus for function decompositionTABULA INC·Filed 2007·Granted Oct 27, 2009·28 cites·20 claims
- 1093US8760193B2Configurable storage elementsVOOGEL MARTIN·Filed 2012·Granted Jun 24, 2014·19 cites·22 claims
- 1193US7971172B1IC that efficiently replicates a function to save logic and routing resourcesTABULA INC·Filed 2008·Granted Jun 28, 2011·22 cites·20 claims
- 1292US8429579B2Translating a user design in a configurable IC for debugging the user designHUTCHINGS BRAD·Filed 2011·Granted Apr 23, 2013·14 cites·16 claims
- 1392US8069425B2Translating a user design in a configurable IC for debugging the user designHUTCHINGS BRAD·Filed 2007·Granted Nov 29, 2011·23 cites·24 claims
- 1492US7609085B1Configurable integrated circuit with a 4-to-1 multiplexerTABULA INC·Filed 2006·Granted Oct 27, 2009·23 cites·28 claims
- 1591US8458629B2Decision modules in integrated circuit designCALDWELL ANDREW·Filed 2010·Granted Jun 4, 2013·13 cites·29 claims
- 1691US6898773B1Method and apparatus for producing multi-layer topological routesCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted May 24, 2005·45 cites·22 claims
- 1790US6895567B1Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted May 17, 2005·43 cites·25 claims
- 1889US8166435B2Timing operations in an IC with configurable circuitsTEIG STEVEN·Filed 2008·Granted Apr 24, 2012·13 cites·22 claims
- 1989US8112733B2Method and apparatus for routing with independent goals on different layersFRANKLE JONATHAN·Filed 2008·Granted Feb 7, 2012·19 cites·26 claims
- 2089US7155697B2Routing method and apparatusCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Dec 26, 2006·20 cites·12 claims
- 2189US6769105B1Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Jul 27, 2004·40 cites·12 claims
- 2288US8863067B1Sequential delay analysis by placement enginesCALDWELL ANDREW·Filed 2008·Granted Oct 14, 2014·17 cites·28 claims
- 2387US8112468B1Method and apparatus for performing an operation with a plurality of sub-operations in a configurable ICREDGRAVE JASON·Filed 2007·Granted Feb 7, 2012·11 cites·7 claims
- 2487US7694083B1System and method for providing a virtual memory architecture narrower and deeper than a physical memory architectureTABULA INC·Filed 2006·Granted Apr 6, 2010·13 cites·22 claims
- 2587US6877146B1Method and apparatus for routing a set of netsCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Apr 5, 2005·48 cites·15 claims
- 2685US8664974B2Operational time extensionROHE ANDRE·Filed 2011·Granted Mar 4, 2014·5 cites·20 claims
- 2785US7480885B2Method and apparatus for routing with independent goals on different layersCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jan 20, 2009·35 cites·22 claims
- 2885US7114141B1Method and apparatus for decomposing a design layoutCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Sep 26, 2006·24 cites·23 claims
- 2985US6957411B1Gridless IC layout and method and apparatus for generating such a layoutCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Oct 18, 2005·39 cites·31 claims
- 3084US9954530B2Implementation of related clocksALTERA CORP·Filed 2015·Granted Apr 24, 2018·5 cites·22 claims
- 3184US6889372B1Method and apparatus for routingCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted May 3, 2005·38 cites·18 claims
- 3284US6829757B1Method and apparatus for generating multi-layer routesCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Dec 7, 2004·40 cites·24 claims
- 3382US9436794B2Sequential timing using level-sensitive clocked elements to optimize IC performanceALTERA CORP·Filed 2014·Granted Sep 6, 2016·4 cites·21 claims
- 3482US6915500B1Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiringCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Jul 5, 2005·22 cites·24 claims
- 3581US9000801B1Implementation of related clocksTABULA INC·Filed 2013·Granted Apr 7, 2015·5 cites·21 claims
- 3681US6889371B1Method and apparatus for propagating a functionCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted May 3, 2005·21 cites·2 claims
- 3780US7107564B1Method and apparatus for routing a set of netsCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Sep 12, 2006·28 cites·22 claims
- 3880US6938234B1Method and apparatus for defining viasCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Aug 30, 2005·28 cites·19 claims
- 3979US8935647B2Decision modulesTABULA INC·Filed 2013·Granted Jan 13, 2015·3 cites·20 claims
- 4079US8463836B1Performing mathematical and logical operations in multiple sub-cyclesPUGH DANIEL J·Filed 2005·Granted Jun 11, 2013·13 cites·30 claims
- 4179US7003752B2Method and apparatus for routingCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Feb 21, 2006·26 cites·30 claims
- 4279US6973634B1IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layoutCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Dec 6, 2005·22 cites·18 claims
- 4378US8555218B2Decision modulesCALDWELL ANDREW·Filed 2009·Granted Oct 8, 2013·6 cites·30 claims
- 4476US8756547B2Timing operations in an IC with configurable circuitsTEIG STEVEN·Filed 2012·Granted Jun 17, 2014·3 cites·21 claims
- 4576US7246338B1Method and apparatus for computing cost of a path expansion to a surfaceCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jul 17, 2007·12 cites·20 claims
- 4676US7036105B1Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC'sCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Apr 25, 2006·19 cites·21 claims
- 4775US7020863B1Method and apparatus for decomposing a region of an integrated circuit layoutCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Mar 28, 2006·11 cites·17 claims
- 4875US6986117B1Method and apparatus for identifying a path between source and target statesCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jan 10, 2006·14 cites·14 claims
- 4975US6859916B1Polygonal viasCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Feb 22, 2005·21 cites·11 claims
- 5074US6957408B1Method and apparatus for routing nets in an integrated circuit layoutCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Oct 18, 2005·19 cites·20 claims
Showing the top 50 of 104 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →