Inventor

STARK DONALD C

US96 patents

⚠️ This page may combine multiple inventors who share the name “STARK DONALD C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STARK DONALD C

RAMBUS INC

Calibrated data communication system and method

Calibrated data communication system and method

Integrated circuit with timing adjustment mechanism and method

Memory device supporting a dynamically configurable core organization

Power control system for synchronous memory device

Single-clock, strobeless signaling system

Bus system optimization

Delay locked loop circuitry for clock delay adjustment

High performance cost optimized memory

Power control system for synchronous memory device

Variable delay element

Delay-locked loop circuitry for clock delay adjustment

High performance cost optimized memory with delayed memory writes

Impedance controlled output driver

High performance cost optimized memory

Memory system with channel multiplexing of multiple memory devices

Power control system for synchronous memory device

Integrated circuit memory device with delayed write command processing

Integrated circuit memory device having write latency function

Delay locked loop circuitry for clock delay adjustment

Single-clock, strobeless signaling system

Asynchronous, high-bandwidth memory component using calibrated timing elements

Charge compensation control circuit and method for use with output driver

Synchronous memory device having a temperature register

Method and apparatus for adjusting the performance of a synchronous memory system

Apparatus and method for pipelined memory operations

Apparatus and method for edge based duty cycle conversion

Memory and method for sensing sub-groups of memory elements

Apparatus and method for bus timing compensation

Memory and method for sensing sub-groups of memory elements

Asynchronous, high-bandwidth memory component using calibrated timing elements

Memory device having a read pipeline and a delay locked loop

Asynchronous, high-bandwidth memory component using calibrated timing elements

Memory system having delayed write timing

Integrated circuit memory device having delayed write timing based on read response time

System and method for aligning internal transmit and receive clocks

Single-clock, strobeless signaling system

Asynchronous, high-bandwidth memory component using calibrated timing elements

Asynchronous, high-bandwidth memory component using calibrated timing elements

Apparatus and method for pipelined memory operations

Apparatus and method for edge based duty cycle conversion

Apparatus and method for maximizing information transfers over limited interconnect resources

Apparatus and method for device timing compensation

Method and apparatus for sharing sense amplifiers between memory banks

Quadrature phase detector

Memory controller that calibrates a transmit timing offset

INTEL CORP

Memory device and system including a low power interface

TOSHIBA KK

Semiconductor memory with bypass circuit

WARE FREDERICK A

Control component for controlling a delay interval within a memory component

TSERN ELY K

Memory device having multiple power modes