Memory and method for sensing sub-groups of memory elements

Abstract

A memory and method of operation is disclosed. In one embodiment, the memory includes a group of memory cells divided into a plurality of subgroups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a subgroup and is coupled to the memory cells in the row of the corresponding subgroup. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit (s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.

What is claimed is:  
     
       1. A memory comprising: 
       a memory array of storage locations;  
       a plurality of word lines for selecting rows of the memory array, each word line comprising a plurality of segments, each segment spanning a portion of the distance of the word line;  
       a plurality of sets of sense amplifiers, each sense amplifier of the sets of sense amplifiers selectively coupled to one storage location associated with the word line, each set of sense amplifiers corresponding to a segment;  
       a first select logic for selecting at least one segment of a word line during a sense operation; and  
       a second select logic for selecting at least one corresponding set of sense amplifiers.  
     
     
       2. The memory as set forth in claim  1 , wherein the memory is located on a component and the first select logic comprises a controller located on the component. 
     
     
       3. The memory as set forth in claim  1 , wherein the memory is located on a component and the second select logic comprises a controller located on the component. 
     
     
       4. The memory as set forth in claim  1 , wherein the first select logic issues a select signal to a gate having as inputs the select signal and a row signal indicative that the row is selected, the output of the gate activating the selected segment when the select signal and the row signal are active. 
     
     
       5. The memory as set forth in claim  1 , wherein the memory further comprises a plurality of gates, an output of each gate coupled to selectively activate a segment, each gate receiving as input a row signal indicative that a row is selected and a select signal indicative that a segment is selected. 
     
     
       6. The memory as set forth in claim  1 , wherein the first select logic comprises a controller which issues a first select signal and a plurality of decoders each coupled to receive the first select signal and selectively activate a segment when row decode logic indicates tat the corresponding row is selected. 
     
     
       7. The memory as set forth in claim  1 , wherein the second select logic issues the following signals: 
       SUBSAP[3:0] and {overscore (SUBSAN)} [3:0] 
       wherein the bits set indicate the set of sense amplifiers that is to be activated. 
     
     
       8. A method for accessing a memory comprising a plurality of storage locations , that includes a plurality of storage locations arranged in rows and word lines for selecting the rows, each word line including a plurality of segments and each segment spanning a portion of the distance of the word line, said method comprising the steps of: 
       providing a plurality of word lines for selecting rows of a memory array, each word line comprising a plurality of segments, each segment spanning a portion of the distance of the word line; 
       identifying sets of sense amplifiers, each sense amplifier of the sets of sense amplifiers coupled to one storage location associated with a word line, each set of sense amplifiers corresponding to a segment;  
       selecting at least one segment of a word line that is to be activated during a sense operation; and  
       selecting at least one corresponding set of sense amplifiers.  
     
     
       9. The method as set forth in claim  8 , wherein the set of selecting a segment comprises the steps of: 
       issuing a segment select signal to identify a segment to be selected;  
       issuing a row select signal to identify a row to be selected;  
       selecting a particular segment in a particular row based on the segment select signal and row select signal issued.  
     
     
       10. The method as set forth in claim  8 , wherein the step of selecting a corresponding set of sense amplifiers comprises the step of issuing a set select signal to select a set of sense amplifiers. 
     
     
       11. The method as set forth in claim  8 , wherein the access performed is a read operation, said method further comprising the steps of: 
       sensing the data of the selected segment, said sense operation placing the data in the corresponding set of sense amplifiers;  
       restoring the data to the selected segment; and  
       performing a column address strobe (CAS) wherein the data in the corresponding set of sense amplifiers is output from the memory.  
     
     
       12. The method as set forth in claim  11 , further comprising the step of precharging the sense amplifiers prior to performing the step of sensing the data. 
     
     
       13. The method as set forth in claim  8 , wherein the access performed is a write operation, said method further comprising the steps of: 
       performing a level word line access, wherein the selected segment remains activated until another segment is selected; and  
       performing a column address strobe (CAS) wherein data to be written is latched into the corresponding set of sense amplifiers, said CAS causing the data to further be stored in storage locations coupled to the selected segment.  
     
     
       14. The method as set forth in claim  8 , wherein the access performed is a write operation, said method further comprising the steps of: 
       performing a pulse word line access, wherein the selected segment is activated prior to performing a sense cycle and restore cycle and deactivated after completion of the restore cycle;  
       performing a column address strobe (CAS) wherein data to be written is latched into the corresponding set of sense amplifiers; and  
       performing an explicit restore operation thereby causing the data located in the corresponding set of sense amplifiers to be stored in storage locations coupled to the selected segment.  
     
     
       15. A memory comprising: 
       a plurality of word lines for selecting a row of a memory array, each word line comprising a plurality of segments, each segment spanning a portion of the distance of the word line;  
       a plurality of sets of sense amplifiers, each sense amplifier of the sets of sense amplifiers selectively coupled to one storage location associated with a word line, each set of sense amplifiers corresponding to a segment;  
       a first select logic for selecting during a sense operation at least one segment from a first word line and at least one segment from a second word line; and  
       a second select logic for selecting corresponding sets of sense amplifiers to access storage locations along the first segment and the second segment.  
     
     
       16. The memory as set forth in claim  15 , wherein the memory is located on a component and the first select logic comprises a controller located on the component. 
     
     
       17. The memory as set forth in claim  15 , wherein the memory is located on a component and the second select logic comprises a controller located on the component. 
     
     
       18. The memory as set forth in claim  15 , wherein the first select logic issues a first select signal to a first gate and a second select signal to a second gate, the first gate and second gate further respectively receiving as input a first row signal and second row signal indicative that the first row and second row, respectively, are selected, the output of the first gate activating the first selected segment when the first select signal and the first row signal are active and the output of the second gate activating the second selected segment when the second select signal and the second row signal are active. 
     
     
       19. The memory as set forth in claim  15 , wherein the memory further comprises a plurality of gates, an output of each gate coupled to selectively activate a segment of a row, each gate receiving as input a row signal indicative that a row is selected and a select signal to indicate selection of a segment in a particular row. 
     
     
       20. The memory as set forth in claim  15 , wherein the first select logic comprises a controller which issues a first select signal and a plurality of decoders each coupled to receive the first select signal and selectively activate a coupled segment when row decode logic indicates that the corresponding row is selected. 
     
     
       21. The memory as set forth in claim  15 , wherein the second select logic issues the following signals: 
       SUBSAP[3:0] and SUBSAN [3:0] 
       wherein the bits set indicate the set of sense amplifiers that is to be activated. 
     
     
       22. A method for accessing a memory comprising a plurality of storage locations  that includes a plurality of storage locations arranged in rows and word lines for selecting the rows, each word line including a plurality of segments and each segment spanning a portion of the distance of the word line, said method comprising the steps of: 
       providing a plurality of word lines for selecting rows of a memory array, each word line comprising a plurality of segments, each segment spanning a portion of the distance of the word line; 
       identifying sets of sense amplifiers, each sense amplifier of the sets of sense amplifiers coupled to one storage location associated with a word line, each set of sense amplifiers corresponding to a segment;  
       selecting at least one segment of a first word line to activate during a sense operation;  
       selecting at least one segment of a second word line that is to be activated during a sense operation; and  
       selecting sets of sense amplifiers corresponding to the at least one segment of the first word line and at least one segment of the second word line to access storage locations along the first segment and the second segment.  
     
     
       23. The method as set forth in claim  22 , wherein: 
       the step of selecting at least one segment of a first word line comprises the steps of issuing a first select signal; and  
       the step of selecting at least one segment of a second word line comprises the step of issuing a second select signal.  
     
     
       24. The method as set forth in claim  22 , further comprising the step of issuing a select signal that identifies at least one segment of at least one row to be selected; 
       wherein the steps of selecting at least one segment of a first word line and at least one segment of a second word line comprise decoding the select signal to determine the segments to select.  
     
     
       25. The method as set forth in claim  22 , wherein the step of selecting sets of sense amplifiers comprises the step of issuing the following signals: 
       SUBSAP[3:0] and SUBSAN [3:0] 
       wherein the bits set indicate the set of sense amplifiers to activate. 
     
     
       26. The method as set forth in claim  22  wherein the access performed is a read operation, said method further comprising the steps of: 
       sensing the data of the selected segments, said sense operation placing the data in the corresponding set of sense amplifiers;  
       restoring the data to the selected segments; and  
       performing a column address strobe (CAS) wherein the data in the corresponding sets of sense amplifiers are output from the memory.  
     
     
       27. The method as set forth in claim  26 , further comprising the step of precharging the sense amplifiers prior to performing the step of sensing the data. 
     
     
       28. The method as set forth in claim  22 , wherein the access performed is a write operation, said method further comprising the steps of: 
       performing a level word line access, wherein the selected segments remains activated until another segment is selected; and  
       performing a column address strobe (CAS) wherein data to be written are latched into the corresponding sets of sense amplifiers, said CAS causing the data to further be stored in storage locations coupled to the selected segments.  
     
     
       29. The method as set forth in claim  22 , wherein the access performed is a write operation, said method further comprising the steps of: 
       performing a pulse word line access, wherein the selected segments are activated prior to performing a sense cycle and restore cycle and deactivated after completion of the restore cycle;  
       performing a column address strobe (CAS) wherein data to be written is latched into the corresponding sets of sense amplifiers; and  
       performing an explicit restore operation thereby causing the data located in the corresponding sets of sense amplifiers to be stored in storage locations coupled to the selected segments.  
     
     
       30. The method as set forth in claim  22 , wherein the access performed is a write operation, said method further comprising the steps of: 
       performing a pulse word line access, wherein the selected segments are activated prior to performing a sense cycle and restore cycle and deactivated after completion of the restore cycle;  
       performing a column address strobe (CAS) wherein data to be written is latched into the corresponding sets of sense amplifiers;  
       performing an explicit restore operation with respect to the first segment thereby causing the data located in the corresponding set of sense amplifiers to be stored in storage locations coupled to the first segment; and  
       performing an explicit restore operation with respect to the the second segment thereby causing the data located in the corresponding set of sense amplifiers to be stored in storage locations coupled to the second segment.  
     
     
       31. A memory comprising: 
       
         storage locations arranged in rows;  
       
         a word line to select a first row of the storage locations, the word line including a plurality of word line segments coupled to enable access to respective sub - groups of the storage locations in the first row; and    
       
         a first selection circuit to selectively activate a variable number of the word line segments in accordance with a control value that indicates a pattern of the word line segments to be activated. 
       
     
     
       32. The memory of claim  31  further comprising a plurality of sets of sense amplifiers, the sets of sense amplifiers coupled respectively to the sub- groups of the storage locations.   
     
     
       33. The memory of claim  32  further comprising a second selection circuit configured to selectively activate a variable number of the sets of sense amplifiers in accordance with the control value. 
     
     
       34. The memory of claim  32  wherein the plurality of sets of sense amplifiers are coupled to the first select circuit and a variable number of the sets of sense amplifiers are activated in accordance with the control value. 
     
     
       35. The memory of claim  32  further comprising a memory address tag to store an address, the address corresponding to a first storage location of the sub- groups of the storage locations.   
     
     
       36. The memory of claim  32  further comprising a valid tag to indicate that data sensed in at least one set of the sets of sense amplifiers is valid. 
     
     
       37. The memory of claim  32  further comprising a dirty tag to indicate that data has been written to the at least one set of the sets of sense amplifiers. 
     
     
       38. The memory of claim  31  further comprising circuitry to receive a sub- group activation signal, the select logic configured to activate the variable number of the word line segments in accordance with the control value if the sub - group activation signal is in a first state.   
     
     
       39. The memory of claim  38  wherein the control value includes a plurality of bits, each bit corresponding to a respective word line segment. 
     
     
       40. The memory of claim  31  further comprising: 
         a second word line to select a second row of the storage locations, the second word line including a second plurality of word line segments each coupled to enable access to a respective sub - group of the storage locations in the second row; and    
       
         select logic to concurrently activate at least one of the word line segments included in the second word line and the variable number of the sets of word line segments in the first row. 
       
     
     
       41. The memory of claim  40  wherein further comprising a row decoder to receive a row address, the row decoder selecting both the first and second word lines in accordance with the row address. 
     
     
       42. A memory comprising: 
       
         a memory array of storage locations  
       
         sense amplifier circuitry, including a plurality of sets of sense amplifiers coupled to respective sub - groups of the storage locations; and    
       
         first selection circuitry to selectively activate a variable number of the sets of sense amplifiers in accordance with a control value that indicates a pattern of the sets of sense amplifiers to be activated. 
       
     
     
       43. The memory of claim  42  further comprising: 
         a word line to select a first row of the storage locations the word line including a plurality of word line segments coupled to enable access to the respective sub - groups of the storage locations in the first row; and    
       
         second selection circuitry to selectively activate a variable number of the word line segments in accordance with the control value. 
       
     
     
       44. The memory of claim  43  further comprising: 
         a second word line to select a second row of the storage locations, the word line including a second plurality of word line segments each coupled to enable access to a respective sub - group of the storage locations in the second row; and    
       
         third selection circuitry to concurrently activate at least one of the word line segments included in the second word line in accordance with the control value. 
       
     
     
       45. The memory of claim  44  further comprising a row decoder to receive a row address, the row decoder selecting both the first and second word lines in accordance with the row address. 
     
     
       46. The memory of claim  42  further comprising a memory address tag to store an address, the address corresponding to a storage location of data sensed in at least one set of the sets of sense amplifiers. 
     
     
       47. The memory of claim  46  further comprising: 
       
         a valid tag to indicate whether the data latched in the at least one set of sense amplifiers is valid. 
       
     
     
       48. The memory of claim  46  further comprising: 
       
         a dirty tag to indicate that data has been written to the at least one set of sense amplifiers. 
       
     
     
       49. A memory comprising: 
       
         storage locations arranged in rows;  
       
         a first word line to select a first row of the storage locations, the first word line including a plurality of word line segments coupled to enable access to respective sub - groups of the storage locations in the first row:    
         a second word line to select a second row of the storage locations, the second word line including a plurality of word line segments coupled to enable access to respective sub - groups of the storage locations in the second row; and    
       
         selection circuitry to concurrently activate a first word line segment included in the first word line and a second word line segments included in the second word line. 
       
     
     
       50. The memory of claim  49  further comprising a row decoder to receive a row address, the row decoder selecting both the first and second word lines in accordance to the row address. 
     
     
       51. The memory of claim  49  further comprising: 
         a first set of sense amplifiers coupled to a first sub - group of storage locations, the first sub - group of storage locations corresponding to the first word line segment included in the first word line; and    
         a second set of sense amplifiers coupled to a second sub - group of storage locations, the second sub - group of storage locations corresponding to the second word line segment included in the second word line.   
     
     
       52. The memory of claim  51  further comprising: 
       
         a memory address tag to store an address, the address corresponding to a storage location address of data sensed in the first set of sense amplifiers;  
       
       
         a valid tag to indicate whether the data sensed in the first set of sense amplifiers is valid; and  
       
       
         a dirty tag to indicate whether the data sensed in the first set of sense amplifiers data has been updated. 
       
     
     
       53. A memory comprising: 
       
         storage locations arranged in rows and columns;  
       
       
         sense amplifiers coupled respectively to the columns of storage locations, the sense amplifiers including first and second sets of sense amplifiers;  
       
         a first word line to select a first row of the storage locations, the first word line including a plurality of word line segments coupled to enable access to respective sub - groups of the storage locations in the first row;    
         a second word line to select a second row of the storage locations, the second word line including a plurality of word line segments coupled to enable access to respective sub - groups of the storage locations in the second row; and    
         selection circuitry to activate at least one of the word line segments included in the first word line to transfer contents of the corresponding sub - group of the storage locations in the first row to the first set of sense amplifiers and to activate at least one of the word line segments included in the second word line to transfer contents of the corresponding sub - group of the storage locations in the second row to the second set of sense amplifiers.   
     
     
       54. The memory of claim  53  further comprising a row decoder to receive a row address and to select both the first and second word lines in accordance with the row address. 
     
     
       55. The memory of claim  54  further comprising: 
       
         a memory address tag to store an address, the address corresponding to a storage location of data latched in the first sets of sense amplifiers;  
       
       
         a first tag to indicate whether the data latched in the first set of sense amplifiers is valid; and  
       
       
         a second tag to indicate whether the data has been written to the first set of sense amplifiers. 
       
     
     
       56. A method of operation in a memory, the method comprising: 
         receiving a control value that indicates sub - groups of a row of storage locations within a first row of the memory; and    
         activating more than one and fewer than all of a plurality of word line segments in accordance with the control value to enable access to the corresponding sub - groups of the storage locations in the first row.   
     
     
       57. The method of claim  56  further comprising storing an address in an address tag, the address being representative of one storage location of the storage locations in the first row. 
     
     
       58. The method of claim  56  wherein the memory further includes a plurality of sets of sense amplifiers each coupled to respective sub- groups of the storage locations in the first row, the method further including transferring data from storage locations corresponding to the activated plurality of word line segments in the first row to the corresponding plurality of sets of sense amplifiers.   
     
     
       59. The method of claim  58  further comprising: 
       
         inputting data from an external signal line;  
       
       
         writing the data to at least one sense amplifier of the plurality of sets of sense amplifiers; and  
       
       
         setting a dirty tag to indicate the writing of data to the at least one sense amplifier. 
       
     
     
       60. The method of claim  56  further comprising activating at least one word line segment of a plurality of word line segments in a second row to enable access to at least one corresponding sub- group of the storage locations in a second row.   
     
     
       61. The method of claim  60  wherein the control value is further indicative of the at least one corresponding sub- group of the storage locations within the second row.   
     
     
       62. The method of claim  56  wherein the memory further comprises a plurality of sets of sense amplifiers coupled to respective sub- groups of storage locations in the first row, the method further comprising:    
       
         transferring data from storage locations corresponding to at least one activated word line segment to a corresponding set of sense amplifiers; and  
       
       
         setting a valid bit to indicate that the data transferred is valid. 
       
     
     
       63. The method of claim  56  wherein the memory further comprises a first set of sense amplifiers coupled to a first sub- group of the storage locations in the first row and a second set of sense amplifiers coupled to a second sub - group of storage locations in a second row, the method further comprising:    
         transferring data corresponding to the first sub - group of the storage locations in the first row to the first set of sense amplifiers; and    
         transferring data corresponding to the second sub - group of storage locations in a second row to the second set of sense amplifiers.   
     
     
       64. The method of claim  56  wherein the control value includes a plurality of bits, each bit corresponding to a respective one of the plurality of word line segments in the first row. 
     
     
       65. The method of claim  56  further comprising receiving a sub- group selection activation signal, wherein the sub - groups of the storage locations in the first row corresponding to the control value are activated in accordance to the control value if the sub - group selection activation signal is in a first state.