Inventor

RICHARDSON WAYNE S

US60 patents

⚠️ This page may combine multiple inventors who share the name “RICHARDSON WAYNE S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RICHARDSON WAYNE S

RAMBUS INC

Chip socket assembly and chip file assembly for semiconductor chips

Memory device comprising programmable command-and-address and/or data interfaces

Integrated circuit memory system having dynamic memory bank count and page size

Multi-column addressing mode memory system including an integrated circuit memory device

Multi-column addressing mode memory system including an integrated circuit memory device

Chip socket assembly and chip file assembly for semiconductor chips

Memory and method for sensing sub-groups of memory elements

Memory and method for sensing sub-groups of memory elements

Communication channel calibration using feedback

Chip socket assembly and chip file assembly for semiconductor chips

Quadrature phase detector

DRAM having a plurality of registers

Protocol for memory power-mode control

Protocol for memory power-mode control

Multi-column addressing mode memory system including an integrated circuit memory device

Multi-column addressing mode memory system including an integrated circuit memory device

Integrated circuit memory device having dynamic memory bank count and page size

Technique for operating a delay circuit

Protocol for memory power-mode control

Protocol for memory power-mode control

Memory device comprising programmable command-and-address and/or data interfaces

Protocol for memory power-mode control

Memory device comprising programmable command-and-address and/or data interfaces

Protocol for memory power-mode control

Protocol for memory power-mode control

Protocol for memory power-mode control

Memory device comprising programmable command-and-address and/or data interfaces

Memory device comprising programmable command-and-address and/or data interfaces

Drift adjustment in timing signal forwarded from memory controller to memory device based on a detected phase delay occurring on a second timing signal with a different frequency

Drift detection in timing signal forwarded from memory controller to memory device

Chip socket assembly and chip file assembly for semiconductor chips

Memory device comprising programmable command-and-address and/or data interfaces

Memory controller for micro-threaded memory operations

Drift detection in timing signal forwarded from memory controller to memory device

Memory device comprising programmable command-and-address and/or data interfaces

Drift detection in timing signal forwarded from memory controller to memory device

Drift detection in timing signal forwarded from memory controller to memory device

Drift detection in timing signal forwarded from memory controller to memory device

Protocol for memory power-mode control

Memory controller for micro-threaded memory operations

Communication channel calibration using feedback

Communication channel calibration using feedback

Pulse multiplexed output system

WARE FREDERICK A

Micro-threaded memory

Multi-column addressing mode memory system including an integrated circuit memory device

ELLIS WAYNE F

Protocol for memory power-mode control

LAI LAWRENCE

Memory device having staggered memory operations

PERINO DONALD V

Chip socket assembly and chip file assembly for semiconductor chips

KASAMSETTY KISHORE VEN

Request-command encoding for reduced-data-rate testing

KIM JUN

Communication channel calibration using feedback