Inventor

LAI LAWRENCE

US60 patents

⚠️ This page may combine multiple inventors who share the name “LAI LAWRENCE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAI LAWRENCE

RAMBUS INC

Memory device comprising programmable command-and-address and/or data interfaces

Multi-column addressing mode memory system including an integrated circuit memory device

Multi-column addressing mode memory system including an integrated circuit memory device

Memory and method for sensing sub-groups of memory elements

Memory and method for sensing sub-groups of memory elements

Memory component that performs data write from pre-programmed register

DRAM having a plurality of registers

Protocol for memory power-mode control

Memory component with error-detect-correct code interface

Protocol for memory power-mode control

Multi-column addressing mode memory system including an integrated circuit memory device

Multi-column addressing mode memory system including an integrated circuit memory device

DRAM output circuitry supporting sequential data capture to reduce core access times

Single command, multiple column-operation memory device

Method and apparatus for testing memory

Protocol for memory power-mode control

Memory component with error-detect-correct code interface

Protocol for memory power-mode control

Memory device comprising programmable command-and-address and/or data interfaces

Memory component with error-detect-correct code interface

Protocol for memory power-mode control

Memory device comprising programmable command-and-address and/or data interfaces

Protocol for memory power-mode control

Protocol for memory power-mode control

Protocol for memory power-mode control

Single command, multiple column-operation memory device

Memory component with error-detect-correct code interface

Memory device comprising programmable command-and-address and/or data interfaces

Memory device comprising programmable command-and-address and/or data interfaces

Communication via a memory interface

Methods and systems for mapping a peripheral function onto a legacy memory interface

Integrated circuit memory device, system and method having interleaved row and column control

Memory device comprising programmable command-and-address and/or data interfaces

Memory controller for micro-threaded memory operations

Methods and systems for mapping a peripheral function onto a legacy memory interface

Methods and systems for mapping a peripheral function onto a legacy memory interface

Integrated circuit memory device, system and method having interleaved row and column control

Memory device comprising programmable command-and-address and/or data interfaces

Command-differentiated storage of internally and externally sourced data

Memory component with error-detect-correct code interface

Protocol for memory power-mode control

Memory controller for micro-threaded memory operations

Memory component with error-detect-correct code interface

Data write from pre-programmed register

WARE FREDERICK A

Micro-threaded memory

Multi-column addressing mode memory system including an integrated circuit memory device

GRAPHIC PACKAGING CORP

Microwave oven heating element having broken loops

(unassigned)

Microwavable container with heating element having energy collecting loops

ELLIS WAYNE F

Protocol for memory power-mode control

LAI LAWRENCE

Memory device having staggered memory operations