Inventor

CHI MIN-HWA

US273 patents

⚠️ This page may combine multiple inventors who share the name “CHI MIN-HWA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHI MIN-HWA

TAIWAN SEMICONDUCTOR MFG

Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications

Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process

Conductor layout technique to reduce stress-induced void formations

Quasi-plannar and FinFET-like transistors on bulk silicon

Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications

Fabrication methods of vertical metal-insulator-metal (MIM) capacitor for advanced embedded DRAM applications

Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials

Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control

Modification of carrier mobility in a semiconductor device

Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control

Storage element and SRAM cell structures using vertical FETS controlled by adjacent junction bias through shallow trench isolation

Gate-controlled, negative resistance diode device using band-to-band tunneling

Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM

Capacitor under bitline (CUB) memory cell structure employing air gap void isolation

Active CMOS pixel with exponential output based on the GIDL mechanism

Method for forming a crown capacitor having HSG for DRAM memory

VANGUARD INT SEMICONDUCT CORP

Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor

Method of making stacked gate memory cell structure

Fabrication method and structure for a DRAM cell with bipolar charge amplification

Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise

Edge triggered delay line, a multiple adjustable delay line circuit, and an application of same

Clock synchronized delay scheme using edge-triggered delay lines and latches with one clock lock time

Operation methods for active BiCMOS pixel for electronic shutter and image-lag elimination

DRAM sensing scheme and isolation circuit

Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor

Bit-line voltage limiting isolation circuit

Fabrication method for a DRAM cell with bipolar charge amplification

NAT SEMICONDUCTOR CORP

Single split-gate MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range

Single MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range

Method for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrate

Single-poly EEPROM cell that is programmable and erasable in a low-voltage environment

Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells

Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell

Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process

GLOBALFOUNDRIES INC

Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices

Methods of forming fins and isolation regions on a FinFET semiconductor device

Fin removal method

FinFETs with air-gap spacers and methods for forming the same

Integrated circuits with replacement metal gates and methods for fabricating the same

Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs

TAIWAN SEMICONDUCTOR MFG CORP

Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate

Method for forming flash memory of ETOX-cell programmed by band-to-band tunneling induced substrate hot electron and read by gate induced drain leakage current

Flash memory cell using p+/N-well diode with double poly floating gate

FOVEON INC

Active pixel image cell with embedded memory and pixel level signal processing capability

Capacitive coupled bipolar active pixel imager having overflow protection and electronic shutter

WORLDWIDE SEMICONDUCTOR MANUFA

Single-poly EEPROM cell structure operations and array architecture

Low voltage low power n-channel flash memory cell using gate induced drain leakage current

FOVEONICS INC

Bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region

JI HUA

Atomic layer deposition method and semiconductor device formed by the same

WORLDWIDE SEMICONDUCTOR MFG

Method for operation of a flash memory using n+/p-well diode