Clock synchronized delay scheme using edge-triggered delay lines and latches with one clock lock time

Abstract

A timing signal synchronization circuit to align an internal timing clock within an integrated circuit with an external system clock with minimum skew and within one cycle of the external system clock is disclosed. A timing signal synchronization circuit has an input buffer subcircuit to receive and delay the external system clock. A fixed delay line circuit is connected to the input buffer subcircuit to delay the received external system clock by a second delay factor to create a first timing signal. The first timing signal is the input to a first and a second measurement delay line. Each will respectively measure a first part and a second part of a period of the first timing signal. A first latch array will receive the measurement and create a first latch signal. A second latch array will receive the measurement and create a second latch signal. A variable delay line will receive the first and second latch signals, and adjust a delay time to values of the measurements of the first and second parts of the period of the first timing signal less the second delay factor. The variable delay line will receive and delay the first timing signal by the delay time to create a second timing signal. An internal buffer subcircuit will receive, buffer, amplify, and delay by a third delay factor the second timing signal to create the internal timing clock that is synchronized with the external system clock.

The invention claimed is: 
     
       1. A timing signal synchronization circuit to synchronize an internal timing signal of an integrated circuit with an external timing signal within one cycle of said external timing signal, comprising: a) an input buffer subcircuit to receive, buffer, and amplify said external timing signal, whereby said input buffer subcircuit has a first delay factor that is a delay time of a received external timing signal from said external timing signal;   b) a fixed delay line circuit connected to the input buffer subcircuit to delay the received external timing signal by a second delay factor to create a first timing signal;   c) a first measurement delay line connected to the fixed delay line to receive the first timing signal, to measure a first part of a period of said first timing signal and to retain said measurement of said first part of said period;   d) a second measurement delay line connected to the fixed delay line to receive the first timing signal, to measure a second part of the period of said first timing signal and to retain said measurement of said second part of said period;   e) a first latch array connected to the first measurement delay line to receive said measurement of the first period and to create a first latch signal;   f) a second latch array connected to the second measurement delay line to receive said measurement of the second period and to create a second latch signal;   g) a variable delay line connected to the first and second latch array to receive the first and second latch signal to adjust a delay time of said variable delay line to values of the measurements of the first and second parts of the period of the first timing signal less the second delay factor, and connected to the fixed delay line to receive the first timing signal and to delay said first timing signal by the delay time said variable delay line to create a second timing signal; and   h) an internal buffer subcircuit to receive, buffer, amplify, and delay by a third delay factor the second timing signal to create the internal timing signal that is synchronized with said external timing signal to circuitry within said integrated circuit.   
     
     
       2. The timing signal synchronization circuit of claim 1 whereby the input buffer subcircuit is a CMOS inverter. 
     
     
       3. The timing signal synchronization circuit of claim 1 wherein the fixed delay line is a plurality of serially cascaded CMOS inverters designed to have a cumulative delay time of the second delay factor. 
     
     
       4. The timing signal synchronization circuit of claim 1 whereby the second delay factor is the sum of the first and third delay factors. 
     
     
       5. The timing signal synchronization circuit of claim 1 wherein the internal buffer subcircuit is a CMOS inverter. 
     
     
       6. A method for synchronizing an internal clock signal within an integrated circuit with an external clock signal within one cycle of an activation of said external clock signal, comprising the steps of: a) receiving and delaying by a first delay factor the external clock to create a first timing signal;   b) delaying the first timing signal by a second delay factor to create a second timing signal;   c) measuring a first part of a period of the second timing signal;   d) measuring a second part of a period of the second timing signal;   e) retaining the measurement of the first part and the second part of the second timing signal;   f) delaying the second timing signal by a sum of the first and second parts of the period to create a third timing signal; and   g) amplifying, buffering, and delaying by a third delay factor said third timing signal for transmission as the internal clock to circuitry within said integrated circuit.   
     
     
       7. The method of claim 6 wherein receiving said external clock signal is in a CMOS inverter. 
     
     
       8. The method of claim 6 wherein delaying the first timing signal is in a fixed delay line that is a plurality of serially cascaded CMOS inverters designed to have a cumulative delay time of the second delay factor. 
     
     
       9. The method of claim 6 whereby the second delay factor is the sum of the first and third delay factors. 
     
     
       10. The method of claim 6 wherein amplifying, buffering, and delaying by the third delay factor said third timing signal is in an internal buffer subcircuit is a CMOS inverter.