P

Inventor

JANG BOR-PING

TW42 patents
⚠️ This page may combine multiple inventors who share the name “JANG BOR-PING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAIWAN SEMICONDUCTOR MFG CO LTD

26 patents
US10157881B2Dec 18, 2018

Methods for controlling warpage in packaging

TAIWAN SEMICONDUCTOR MFG CO LTD9 citations84
US10056285B2Aug 21, 2018

Semiconductor wafer device and manufacturing method thereof

TAIWAN SEMICONDUCTOR MFG CO LTD4 citations84
US9768142B2Sep 19, 2017

Mechanisms for forming bonding structures

TAIWAN SEMICONDUCTOR MFG CO LTD7 citations84
US9659891B2May 23, 2017

Semiconductor device having a boundary structure, a package on package structure, and a method of making

TAIWAN SEMICONDUCTOR MFG CO LTD4 citations84
US9484226B2Nov 1, 2016

Methods for controlling warpage in packaging

TAIWAN SEMICONDUCTOR MFG CO LTD5 citations84
US10510712B2Dec 17, 2019

Methods for controlling warpage in packaging

TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73
US10276531B2Apr 30, 2019

Semiconductor device having a boundary structure, a package on package structure, and a method of making

TAIWAN SEMICONDUCTOR MFG CO LTD1 citations73
US10020211B2Jul 10, 2018

Wafer-level molding chase design

TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73
US11390000B2Jul 19, 2022

Wafer level transfer molding and apparatus for performing the same

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations63
US9893044B2Feb 13, 2018

Wafer-level underfill and over-molding

TAIWAN SEMICONDUCTOR MFG CO LTD1 citations63
US9812346B2Nov 7, 2017

Semiconductor wafer device and manufacturing method thereof

TAIWAN SEMICONDUCTOR MFG CO LTD1 citations63
US11721555B2Aug 8, 2023

Method and system for thinning wafer thereof

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11233032B2Jan 25, 2022

Mechanisms for forming bonding structures

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11139177B2Oct 5, 2021

Method of fabricating semiconductor package structure

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11094561B2Aug 17, 2021

Semiconductor package structure

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11024618B2Jun 1, 2021

Wafer-level underfill and over-molding

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US10985135B2Apr 20, 2021

Methods for controlling warpage in packaging

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US10804234B2Oct 13, 2020

Semiconductor device having a boundary structure, a package on package structure, and a method of making

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US10770331B2Sep 8, 2020

Semiconductor wafer device and manufacturing method thereof

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US10727074B2Jul 28, 2020

Method and system for thinning wafer thereof

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US10679866B2Jun 9, 2020

Interconnect structure for semiconductor package and method of fabricating the interconnect structure

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US10513070B2Dec 24, 2019

Wafer level transfer molding and apparatus for performing the same

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US10504870B2Dec 10, 2019

Mechanisms for forming bonding structures

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US10134703B2Nov 20, 2018

Package on-package process for applying molding compound

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9802349B2Oct 31, 2017

Wafer level transfer molding and apparatus for performing the same

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9129899B2Sep 8, 2015

Method and system for thinning wafer thereof

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52

TAIWAN SEMICONDUCTOR MFG

11 patents

JANG BOR-PING

2 patents

LIN CHIH-WEI

1 patent

CHEN MENG-TSE

1 patent

HSIAO YI-LI

1 patent