Packaging methods and structures for semiconductor devices

Abstract

Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.

What is claimed is: 
     
       1. A method comprising:
 forming a redistribution layer (RDL) comprising at least one inter-level dielectric (ILD) and at least one first metallization layer formed in the at least one ILD; 
 coupling a first integrated circuit to a first surface of the RDL, the first integrated circuit in electrical contact with first traces of the at least one first metallization layer; 
 forming a first molding compound over the first integrated circuit and the first surface of the RDL, a first surface of the first molding compound disposed above a top surface of the first integrated circuit; 
 forming a second metallization layer having second traces on the first surface of the first molding compound, the second traces in electrical contact with the first traces; 
 coupling a second integrated circuit to the second traces; and 
 forming a second molding compound over the second integrated circuit and in direct contact with a portion of the first surface of the first molding compound. 
 
     
     
       2. The method of  claim 1 , further comprising forming vertical connections over the RDL prior to the forming the first molding compound;
 wherein the forming the first molding compound comprises forming the first molding compound around the vertical connections; and 
 wherein the forming the second metallization layer comprises forming the second traces in electrical contact with the first traces through the vertical connections. 
 
     
     
       3. The method according to  claim 1 , wherein the first integrated circuit comprises through vias;
 wherein the forming the first molding compound comprises removing a portion of first integrated circuit, thus exposing the through vias; and 
 wherein the forming the second metallization layer comprises forming the second traces in electrical contact with the through vias. 
 
     
     
       4. The method of  claim 1 , wherein the RDL is formed on a carrier prior to the coupling the first integrated circuit to the first surface of the RDL and prior to the forming the first molding compound over the first integrated circuit. 
     
     
       5. The method of  claim 1 , wherein a portion of the second integrated circuit extends directly over a portion of the first integrated circuit. 
     
     
       6. The method of  claim 1 , further comprising forming conductive metal bumps on a second surface of the RDL opposite the first surface. 
     
     
       7. The method of  claim 1 , wherein the second molding compound extends below a topmost surface of the second traces. 
     
     
       8. A method comprising:
 forming a redistribution layer (RDL) having first traces disposed in a dielectric layer, a portion of the first traces exposed at a first surface of the RDL; 
 forming vertical connections over the RDL, the vertical connections being electrically coupled to the first traces at the first surface of the RDL; 
 mounting a first integrated circuit to the first surface of the RDL, the first integrated circuit electrically coupled to the first traces; 
 forming a first molding compound over the first integrated circuit and the first surface of the RDL, the first molding compound extending around the vertical connections and above the first integrated circuit; 
 forming second traces over the first molding compound and vertical connections, the second traces having portions extending laterally over the first molding compound from the vertical connections; 
 coupling a second integrated circuit to the second traces, the second integrated circuit being electrically connected to the first traces through the second traces and the vertical connections; and 
 forming a second molding compound over the second integrated circuit and the second traces, the second molding compound in contact with the first molding compound. 
 
     
     
       9. The method of  claim 8 , wherein the forming the first molding compound comprises planarizing a first surface of the first molding compound such that the first surface of the first molding compound is substantially planar with first surfaces of the vertical connections. 
     
     
       10. The method of  claim 9 , wherein the forming the second traces over the first molding compound and vertical connections comprises forming portions of the second traces in direct contact with the first surfaces of the vertical connections. 
     
     
       11. The method according to  claim 8 , wherein the first integrated circuit comprises through vias; and
 wherein the forming the first molding compound comprises planarizing a first surface of the first molding compound and a first surface of the first integrated circuit such that the first surface of the first molding compound is substantially planar with first surfaces of the through vias. 
 
     
     
       12. The method according to  claim 11 , wherein the forming the second traces comprising forming portions of the second traces in contact with the first surfaces of the through vias. 
     
     
       13. The method of  claim 8 , wherein the RDL is formed on a carrier prior to the coupling the first integrated circuit to the first surface of the RDL and prior to the forming the first molding compound over the first integrated circuit. 
     
     
       14. The method of  claim 8 , wherein a portion of the second integrated circuit extends directly over a portion of the first integrated circuit. 
     
     
       15. The method of  claim 8 , wherein the second molding compound extends between the second traces. 
     
     
       16. A method comprising:
 forming a redistribution layer (RDL) comprising a plurality of inter-level dielectrics (ILDs) each having a metallization layer formed therein; 
 forming vertical connectors over the RDL, the vertical connections being electrically coupled to first traces in the metallization layers; 
 forming a first molding compound over the RDL, the first molding compound extending around the vertical connectors; 
 removing a portion of the first molding compound and exposing first ends of the vertical connections; 
 forming second traces on the first molding compound and on the first ends of the vertical connections; 
 coupling an integrated circuit to the second traces, the integrated circuit being electrically connected to the first traces in the RDL through the vertical connections; and 
 forming a second molding compound over the integrated circuit and the second traces, second molding compound in direct contact with a portion of the first molding compound. 
 
     
     
       17. The method of  claim 16 , wherein a portion of the second molding compound extends between the second traces to directly contact the portion of the first molding compound. 
     
     
       18. The method of  claim 16 , wherein the forming second traces on the first molding compound and vertical connections comprises forming portions of the second traces in direct contact with the first ends of the vertical connections. 
     
     
       19. The method of  claim 16 , wherein the RDL is formed on a carrier prior the forming the first molding compound over the RDL. 
     
     
       20. The method of  claim 16 , further comprising forming conductive metal bumps on the RDL opposite the vertical connections.