Inventor

KIRKPATRICK BRIAN K

US52 patents

⚠️ This page may combine multiple inventors who share the name “KIRKPATRICK BRIAN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIRKPATRICK BRIAN K

TEXAS INSTRUMENTS INC

Gate dielectric first replacement gate processes and integrated circuits therefrom

Pre-pattern surface modification for low-k dielectrics using A H2 plasma

High-k / metal gate CMOS transistors with TiN gates

Gate dielectric first replacement gate processes and integrated circuits therefrom

High-k / metal gate CMOS transistors with TiN gates

Post high-k dielectric/metal gate clean

Post high voltage gate dielectric pattern plasma surface treatment

Post high voltage gate oxide pattern high-vacuum outgas surface treatment

Selective nitride etching with silicate ion pre-loading

Post plasma clean process for a hardmask

Method to reduce charge interface traps and channel hot carrier degradation

Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom

Cross-contamination control for semiconductor process flows having metal comprising gate electrodes

Nitride removal while protecting semiconductor surfaces for forming shallow junctions

Dual-gate integrated circuit semiconductor device

Protection of silicon from phosphoric acid using thick chemical oxide

Nickel silicide—silicon nitride adhesion through surface passivation

Method of fabricating semiconductors

Reduced semiconductor wafer bow and warpage

Method for stripping one or more layers from a semiconductor wafer

Integrated circuit having chemically modified spacer surface

Integrated circuit having chemically modified spacer surface

MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls

Post high voltage gate oxide pattern high-vacuum outgas surface treatment

Pre-pattern surface modification of low-k dielectrics

Inner L-spacer for replacement gate flow

Inner L-spacer for replacement gate flow

Inner L-spacer for replacement gate flow

Inner L-spacer for replacement gate flow

Systems and methods for removing wafer edge residue and debris using a residue remover mechanism

Method of fabricating semiconductors

Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits

Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits

Dopant anneal with stabilization step for IC with matched devices

Split gate memory cell fabrication and system

Cross-contamination control for processing of circuits comprising MOS devices that include metal comprising high-K dielectrics

Method for improving a physical property defect value of a gate dielectric

Hard mask for source/drain epitaxy control

APPLIED MATERIALS INC

Integratead wet clean for bevel treatments

Cleaning method with in-line SPM processing

Surface cleaning with directed high pressure chemistry

Cleaning system with in-line SPM processing

Integrated wet clean for gate stack development

Integrated wet clean for epitaxial growth

KIRKPATRICK BRIAN K

Method of forming MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls

Die having coefficient of thermal expansion graded layer

Integrated circuit having chemically modified spacer surface

Curvature reduction for semiconductor wafers

BARNA GABRIEL GEORGE

Recessed STI for wide transistors

PRINS STEVEN L

Wafer planarity control between pattern levels