Inventor

PARK JOODONG

US42 patents

⚠️ This page may combine multiple inventors who share the name “PARK JOODONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARK JOODONG

INTEL CORP

Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process

High voltage three-dimensional devices having dielectric liners

Transistor architecture having extended recessed spacer and source/drain regions and method of making same

Transistor with airgap spacer

Dual height glass for finFET doping

CMOS-compatible polycide fuse structure and method of fabricating same

Non-planar semiconductor device having self-aligned fin with top blocking layer

Antifuse element utilizing non-planar topology

Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same

Transistor with dual-gate spacer

Transistor with inner-gate spacer

Vertical non-planar semiconductor device for system-on-chip (SoC) applications

Methods of integrating multiple gate dielectric transistors on a tri-gate (finfet) process

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

Variable pitch and stack height for high performance interconnects

Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

Metal resistor and self-aligned gate edge (SAGE) architecture having a metal resistor

Transistor with thermal performance boost

Asymmetric spacer for low capacitance applications

Transistor with inner-gate spacer

Transistor with an airgap spacer adjacent to a transistor gate

Compound lateral resistor structures for integrated circuitry

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

Vertical non-planar semiconductor device for system-on-chip (SoC) applications

High voltage three-dimensional devices having dielectric liners

Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM)

Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same

Multi voltage threshold transistors through process and design-induced multiple work functions

Dual layer hard mask for block salicide poly resistor (BSR) patterning

Ultra-scaled fin pitch having dual gate dielectrics

HAFEZ WALID M

Antifuse element utilizing non-planar topology

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

YEH JENG-YA D

Precision resistor for non-planar semiconductor device architecture

Precision resistor for non-planar semiconductor device architecture

TSAI CURTIS

Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process

CJ CHEILJEDANG CORP

Laver-snack made of laver and cereal sheets and process of producing the same

JAN CHIA-HONG

Multi-gate transistors