Inventor

BANDYOPADHYAY BASAB

US56 patents

⚠️ This page may combine multiple inventors who share the name “BANDYOPADHYAY BASAB”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BANDYOPADHYAY BASAB

ADVANCED MICRO DEVICES INC

Dissolvable dielectric method

Substantially planar semiconductor topography using dielectrics and chemical mechanical polish

Method of formation of an air gap within a semiconductor dielectric by solvent desorption

Stepper alignment mark structure for maintaining alignment integrity

Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines

Interlevel dielectric with air gaps to reduce permitivity

Interlevel dielectric with air gaps to lessen capacitive coupling

Shallow trench isolation formation without planarization mask

Shallow trench isolation formation with reduced polish stop thickness

Method for achieving global planarization by forming minimum mesas in large field areas

Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

Interlevel dielectric with air gaps to lessen capacitive coupling

Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

Wafer cleaning procedure useful in the manufacture of a non-volatile memory device

Shallow trench isolation formation with ion implantation

Dielectric having an air gap formed between closely spaced interconnect lines

Shallow trench isolation formation with spacer-assisted ion implantation

Shallow trench isolation with spacers for improved gate oxide quality

Shallow trench isolation formation with simplified reverse planarization mask

Dissolvable dielectric method and structure

Shallow trench isolation formation with trench wall spacer

Method of planarizing a semiconductor topography using multiple polish pads

Method of making an integrated circuit with oxidizable trench liner

Integrated circuit having local interconnect for reducing signal cross coupled noise

Integrated circuit which uses a damascene process for producing staggered interconnect lines

Semiconductor interlevel dielectric having a polymide for producing air gaps

Method of forming a recessed interconnect structure

Integrated circuit having local interconnect for reduing signal cross coupled noise

Semiconductor topography employing a shallow trench isolation structure with an improved trench edge

Simplified shallow trench isolation formation with no polish stop

Shallow trench isolation formation with improved trench edge oxide

Shallow trench isolation formation with two source/drain masks and simplified planarization mask

Method of manufacturing a semiconductor device with improved isolation region to active region topography

Integrated circuit having interconnect lines separated by a dielectric having a capping layer

Integrated circuit which uses a damascene process for producing staggered interconnect lines

Integrated circuit having conductors of enhanced cross-sectional area

Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer

Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines

Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization

Integrated circuit having conductors of enhanced cross-sectional area

Integrated circuit having horizontally and vertically offset interconnect lines

Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process

Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer

Method for forming semiconductor field region dielectrics having globally planarized upper surfaces

Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization

Method of manufacturing subfield conductive layer

Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization

Method of forming source/drain regions in a semiconductor device

Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

ADVANCED MICRO DEVCIES INC

Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect