Method of manufacturing subfield conductive layer

Abstract

A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

What is claimed is: 
     
       1. A method for forming a conductive layer, comprising: providing an integrated circuit topography which includes a field dielectric interposed between a pair of active areas;   applying a masking layer over said active areas a spaced distance from said field dielectric to form a partially masked integrated circuit topography;   implanting first dopant ions entirely across said partially masked integrated circuit topography to form a conductive layer in regions below and adjacent to said field dielectric; and   implanting second dopant ions of the same conductivity type as said first dopant ions into source and drain regions configured adjacent said field dielectric in electrical communication with said conductive layer.   
     
     
       2. The method as recited in claim 1, wherein said field dielectric comprises a thermally grown oxide. 
     
     
       3. The method as recited in claim 1, wherein said providing step comprises providing a silicon surface between said active areas, and then thermally growing an oxide upon said silicon surface. 
     
     
       4. The method as recited in claim 1, wherein said field dielectric comprises a trench formed within a substrate thereafter filled with a deposited oxide. 
     
     
       5. The method as recited in claim 1, wherein said providing step comprises etching a substantially planar silicon surface to form a trench therein, and then filling said trench with a chemical vapor deposited oxide. 
     
     
       6. The method as recited in claim 1, wherein said applying step comprises depositing a photoresist layer across said integrated circuit topography and then selectively removing said photoresist layer from said field dielectric. 
     
     
       7. The method as recited in claim 1, wherein said spaced distance is 0.2 to 2.0 microns. 
     
     
       8. The method as recited in claim 1, wherein the step of depositing said first dopant ions comprises implanting at a concentration between 1×10 15  to 1×10 16  ions/cm 2  and at an energy exceeding 350 keV. 
     
     
       9. The method as recited in claim 1, wherein said first dopant ions and said second dopant ions comprise n-type ions implanted into a p-type silicon substrate. 
     
     
       10. The method as recited in claim 1, wherein said first dopant ions and said second dopant ions comprise p-type ions implanted into an n-type silicon substrate.