Inventor

BRENNAN WILLIAM S

US55 patents

⚠️ This page may combine multiple inventors who share the name “BRENNAN WILLIAM S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRENNAN WILLIAM S

ADVANCED MICRO DEVICES INC

Closed loop residual gas analyzer process control technique

Dissolvable dielectric method

Substantially planar semiconductor topography using dielectrics and chemical mechanical polish

Method of formation of an air gap within a semiconductor dielectric by solvent desorption

Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines

Interlevel dielectric with air gaps to reduce permitivity

Interlevel dielectric with air gaps to lessen capacitive coupling

Method for achieving global planarization by forming minimum mesas in large field areas

Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

Interlevel dielectric with air gaps to lessen capacitive coupling

Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

Transistor having a gate stick comprised of a metal, and a method of making same

Dielectric having an air gap formed between closely spaced interconnect lines

Dissolvable dielectric method and structure

Method of planarizing a semiconductor topography using multiple polish pads

Method of making an integrated circuit with oxidizable trench liner

Integrated circuit having local interconnect for reducing signal cross coupled noise

Integrated circuit which uses a damascene process for producing staggered interconnect lines

Semiconductor interlevel dielectric having a polymide for producing air gaps

Method of forming a recessed interconnect structure

Integrated circuit having local interconnect for reduing signal cross coupled noise

Method for forming openings for conductive interconnects

Method for forming copper interconnects

Apparatus and method for measuring liquid level in a sealed container

Method and apparatus for controlling copper barrier/seed deposition processes

Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques

Contact each methodology and integration scheme

CVD Tin Barrier process with improved contact resistance

Semiconductor fabrication employing a conformal layer of CVD deposited TiN at the periphery of an interconnect

Integrated circuit having interconnect lines separated by a dielectric having a capping layer

Integrated circuit which uses a damascene process for producing staggered interconnect lines

Integrated circuit having conductors of enhanced cross-sectional area

Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer

Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines

Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization

Integrated circuit having conductors of enhanced cross-sectional area

Integrated circuit having horizontally and vertically offset interconnect lines

Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process

Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer

Method for forming semiconductor field region dielectrics having globally planarized upper surfaces

Method of manufacturing subfield conductive layer

Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization

Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization

Test structure for providing depth of polish feedback

Thin titanium film as self-regulating filter for silicon migration into aluminum metal lines

Method of improving vacuum quality in semiconductor processing chambers

Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

Substantially planar semiconductor topography using dielectrics and chemical mechanical polish

ADVANCED MICRO DEVCIES INC

Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

ADVANCED MICRO SERVICES

Semiconductor device having silicide layers formed using a collimated metal layer