P

Inventor

KUMAR AKHILESH

US64 patents
⚠️ This page may combine multiple inventors who share the name “KUMAR AKHILESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

21 patents
US6487643B1Nov 26, 2002

Method and apparatus for preventing starvation in a multi-node architecture

INTEL CORP83 citations98
US6971098B2Nov 29, 2005

Method and apparatus for managing transaction requests in a multi-node architecture

INTEL CORP88 citations97
US6615319B2Sep 2, 2003

Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture

INTEL CORP95 citations97
US7234029B2Jun 19, 2007

Method and apparatus for reducing memory latency in a cache coherent multi-node architecture

INTEL CORP27 citations92
US7124252B1Oct 17, 2006

Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system

INTEL CORP28 citations92
US6842830B2Jan 11, 2005

Mechanism for handling explicit writeback in a cache coherent multi-node architecture

INTEL CORP39 citations92
US6772298B2Aug 3, 2004

Method and apparatus for invalidating a cache line without data return in a multi-node architecture

INTEL CORP24 citations92
US7433985B2Oct 7, 2008

Conditional and vectored system management interrupts

INTEL CORP36 citations90
US7016304B2Mar 21, 2006

Link level retry scheme

INTEL CORP25 citations90
US7738484B2Jun 15, 2010

Method, system, and apparatus for system level initialization

INTEL CORP8 citations84
US6859864B2Feb 22, 2005

Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line

INTEL CORP14 citations84
US7996625B2Aug 9, 2011

Method and apparatus for reducing memory latency in a cache coherent multi-node architecture

INTEL CORP10 citations83
US7734741B2Jun 8, 2010

Method, system, and apparatus for dynamic reconfiguration of resources

INTEL CORP10 citations83
US7991875B2Aug 2, 2011

Link level retry scheme

INTEL CORP10 citations81
US7167957B2Jan 23, 2007

Mechanism for handling explicit writeback in a cache coherent multi-node architecture

INTEL CORP9 citations73
US6826619B1Nov 30, 2004

Method and apparatus for preventing starvation in a multi-node architecture

INTEL CORP11 citations72
US9798556B2Oct 24, 2017

Method, system, and apparatus for dynamic reconfiguration of resources

INTEL CORP3 citations70
US9250679B2Feb 2, 2016

Reduced wake up delay for on-die routers

INTEL CORP4 citations70
US6976129B2Dec 13, 2005

Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture

INTEL CORP5 citations63
US6622215B2Sep 16, 2003

Mechanism for handling conflicts in a multi-node computer architecture

INTEL CORP4 citations62
US7370135B2May 6, 2008

Band configuration agent for link based computing system

INTEL CORP2 citations58

ADOBE INC

9 patents

ANSYS INC

6 patents

WISCONSIN ALUMNI RES FOUND

4 patents

AYYAR MANI

3 patents

CHERUKURI NAVEEN

1 patent

TOYO ENGINEERING CORP

1 patent

WENZEL ROBERTO

1 patent

SOARES LIVIO B

1 patent

PARK DONGKOOK

1 patent

THANTRY HARIHARAN

1 patent

PARK SEUNGJOON

1 patent

Showing the top 50 of 64 patents by PatentIndex Score.