Systems and methods for machine learning based fast static thermal solver

Abstract

Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network. The trained predictor can be used to determine a temperature rise and then can be appended to a system level thermal profile of the IC to generate a detailed thermal profile of the IC.

What is claimed is: 
     
       1. A non-transitory machine readable medium storing executable program instructions which when executed by a data processing system cause the data processing system to perform a method, the method comprising:
 generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template comprising a plurality of tiles including a center tile, and each template associated with location parameters to position the template in the IC; 
 performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the IC, the power pattern corresponding to a set of power levels powered on the tiles of the respective template for the thermal simulations, each tile of the respective template powered according to one of the set of power levels, each power level selected from a set of predefined power levels; and 
 training a neural network with a plurality of training data generated via the thermal simulations, each training data including the location parameters of one of the templates for inputs to the neural network and including an output of one of the thermal simulations for the one template. 
 
     
     
       2. The medium as in  claim 1 , wherein the training provides a trained temperature rise predictor. 
     
     
       3. The medium as in  claim 2 , wherein the two or more templates comprise a template along an edge of the IC and a template near a center of the IC. 
     
     
       4. The medium as in  claim 1 , wherein the two or more templates include three templates on the IC. 
     
     
       5. The medium as in  claim 1 , wherein tiles located outside of each template are powered with an average power level during the thermal simulations. 
     
     
       6. The medium as in  claim 1 , wherein the thermal simulations are performed for each template separately and wherein the thermal simulations include computational fluid dynamics simulations or finite element simulations. 
     
     
       7. The medium as in  claim 1 , wherein the performing thermal simulations for each respective template of the IC is based on the location parameters and a relationship between a change in temperature relative to a power applied to the IC in the thermal simulations. 
     
     
       8. The medium as in  claim 7 , wherein the relationship between a change in temperature relative to power is Theta-JA. 
     
     
       9. The medium as in  claim 7 , wherein the relationship between a change in temperature relative to power used in the thermal simulations is varied across the thermal simulations. 
     
     
       10. The medium as in  claim 1 , wherein the set of predefined power levels include three or more power levels. 
     
     
       11. The medium as in  claim 1 , wherein the tiles of each template located outside a border of the IC is powered with a zero power level during the thermal simulations. 
     
     
       12. The medium as in  claim 1 , wherein each template is divided into a center tile group and a ring tile group.