Inventor

BLATCHFORD JAMES WALTER

US45 patents

⚠️ This page may combine multiple inventors who share the name “BLATCHFORD JAMES WALTER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BLATCHFORD JAMES WALTER

TEXAS INSTRUMENTS INC

Gate critical dimension variation by use of ghost features

Method to ensure double patterning technology compliance in standard cells

Method for ensuring DPT compliance with autorouted metal layers

Hybrid pitch-split pattern-split lithography process

System and method for making photomasks

Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two

Method to form silicide and contact at embedded epitaxial facet

Elongated contacts using litho-freeze-litho-etch process

Elongated contacts using litho-freeze-litho-etch process

Two-print two-etch method for enhancement of CD control using ghost poly

Method for ensuring DPT compliance for auto-routed via layers

Gate CD control using local design on both sides of neighboring dummy gate level features

SRAM layout for double patterning

Elongated contacts using litho-freeze-litho-etch process

Metal on elongated contacts

Two-track cross-connect in double-patterned structure using rectangular via

Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements

EDA methodology for extending ghost feature beyond notched active to improve adjacent gate CD control using a two-print-two-etch approach

Method of achieving dense-pitch interconnect patterning in integrated circuits

System for controlling SiGe-to-gate spacing

SRAM layout for double patterning

SRAM layout for double patterning

SRAM layout for double patterning

Layout method to minimize context effects and die area

Perturbational technique for co-optimizing design rules and illumination conditions for lithography process

Gate CD control using local design on both sides of neighboring dummy gate level features

Metal on elongated contacts

Method to form silicide and contact at embedded epitaxial facet

Method to form silicide and contact at embedded epitaxial facet

Method for layout of random via arrays in the presence of strong pitch restrictions

Use of dual mask processing of different composition such as inorganic/organic to enable a single poly etch using a two-print-two-etch approach

Methods for adjusting shifter width of an alternating phase shifter having variable width

BLATCHFORD JAMES WALTER

Two-track cross-connects in double-patterned metal layers using a forbidden zone

Dual alignment strategy for optimizing contact layer alignment

Pattern-split decomposition strategy for double-patterned lithography process

Gate CD control using local design on both sides of neighboring dummy gate level features

Rectangular via for ensuring via yield in the absence of via redundancy

Method for generating ultra-short-run-length dummy poly features

Perturbational technique for co-optimizing design rules and illumination conditions for lithography process

Manufacturability enhancements for gate patterning process using polysilicon sub layer

Two-track cross-connect in double-patterned structure using rectangular via

ICs with end gates having adjacent electrically connected field poly

RATHSACK BENJAMEN MICHAEL

Layout of printable assist features to aid transistor control

GU YIMING

Gate line edge roughness reduction by using 2P/2E process together with high temperature bake

BALDWIN GREGORY CHARLES

Flexible integration of logic blocks with transistors of different threshold voltages