Inventor

HAKEY MARK C

US161 patents

Patents

50 patents

US8004024B2Aug 23, 2011

Method and apparatus for cleaning a semiconductor substrate in an immersion lithography system

IBM62 citations98

US6590258B2Jul 8, 2003

SIO stacked DRAM logic

IBM184 citations98

US6544837B1Apr 8, 2003

SOI stacked DRAM logic

IBM474 citations98

US6387783B1May 14, 2002

Methods of T-gate fabrication using a hybrid resist

IBM134 citations98

US6506660B2Jan 14, 2003

Semiconductor with nanoscale features

IBM101 citations97

US6184151B1Feb 6, 2001

Method for forming cornered images on a substrate and photomask formed thereby

IBM92 citations97

US6627477B1Sep 30, 2003

Method of assembling a plurality of semiconductor devices having different thickness

IBM68 citations96

US6531724B1Mar 11, 2003

Borderless gate structures

IBM37 citations96

US6429045B1Aug 6, 2002

Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage

IBM74 citations96

US6358813B1Mar 19, 2002

Method for increasing the capacitance of a semiconductor capacitors

IBM56 citations96

US6338934B1Jan 15, 2002

Hybrid resist based on photo acid/photo base blending

IBM126 citations96

US6184549B1Feb 6, 2001

Trench storage dynamic random access memory cell with vertical transfer device

IBM47 citations96

US6121651ASep 19, 2000

Dram cell with three-sided-gate transfer device

IBM68 citations96

US6114082ASep 5, 2000

Frequency doubling hybrid photoresist having negative and positive tone components and method of preparing the same

IBM81 citations96

US6107133AAug 22, 2000

Method for making a five square vertical DRAM cell

IBM71 citations96

US6037194AMar 14, 2000

Method for making a DRAM cell with grooved transfer device

IBM82 citations96

US6007968ADec 28, 1999

Method for forming features using frequency doubling hybrid resist and device formed thereby

IBM47 citations96

US5998835ADec 7, 1999

High performance MOSFET device with raised source and drain

IBM50 citations96

US5776660AJul 7, 1998

Fabrication method for high-capacitance storage node structures

IBM64 citations96

US7256415B2Aug 14, 2007

Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells

IBM49 citations95

US6190988B1Feb 20, 2001

Method for a controlled bottle trench for a dram storage node

IBM64 citations95

US5959325ASep 28, 1999

Method for forming cornered images on a substrate and photomask formed thereby

IBM43 citations95

US7585614B2Sep 8, 2009

Sub-lithographic imaging techniques and processes

IBM28 citations93

US7459013B2Dec 2, 2008

Chemical and particulate filters containing chemically modified carbon nanotube structures

IBM23 citations93

US7358120B2Apr 15, 2008

Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM

IBM25 citations93

US7352607B2Apr 1, 2008

Non-volatile switching and memory devices using vertical nanotubes

IBM21 citations93

US7265013B2Sep 4, 2007

Sidewall image transfer (SIT) technologies

IBM25 citations93

US7233071B2Jun 19, 2007

Low-k dielectric layer based upon carbon nanostructures

IBM33 citations93

US7071047B1Jul 4, 2006

Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions

IBM19 citations93

US6846727B2Jan 25, 2005

Patterned SOI by oxygen implantation and annealing

IBM29 citations93

US6596597B2Jul 22, 2003

Method of manufacturing dual gate logic devices

IBM18 citations93

US6489207B2Dec 3, 2002

Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor

IBM38 citations93

US6372412B1Apr 16, 2002

Method of producing an integrated circuit chip using frequency doubling hybrid photoresist and apparatus formed thereby

IBM16 citations93

US6333229B1Dec 25, 2001

Method for manufacturing a field effect transitor (FET) having mis-aligned-gate structure

IBM42 citations93

US6333533B1Dec 25, 2001

Trench storage DRAM cell with vertical three-sided transfer device

IBM20 citations93

US6323082B1Nov 27, 2001

Process for making a DRAM cell with three-sided gate transfer

IBM35 citations93

US6319759B1Nov 20, 2001

Method for making oxide

IBM22 citations93

US6313492B1Nov 6, 2001

Integrated circuit chip produced by using frequency doubling hybrid photoresist

IBM22 citations93

US6303272B1Oct 16, 2001

Process for self-alignment of sub-critical contacts to wiring

IBM50 citations93

US6245488B1Jun 12, 2001

Method for forming features using frequency doubling hybrid resist and device formed thereby

IBM15 citations93

US6210866B1Apr 3, 2001

Method for forming features using self-trimming by selective etch and device formed thereby

IBM22 citations93

US6207540B1Mar 27, 2001

Method for manufacturing high performance MOSFET device with raised source and drain

IBM20 citations93

US6207493B1Mar 27, 2001

Formation of out-diffused bitline by laser anneal

IBM16 citations93

Showing the top 50 of 161 patents by PatentIndex Score.

HAKEY MARK C

Patents

Field effect transistor

Accessible chip stack and process of manufacturing thereof

Structure for folded architecture pillar memory cell

Trench storage dynamic random access memory cell with vertical transfer device

Structure for folded architecture pillar memory cell

Method for forming pillar memory cells and device formed thereby

DRAM cell with grooved transfer device

Method and apparatus for cleaning a semiconductor substrate in an immersion lithography system

SIO stacked DRAM logic

SOI stacked DRAM logic

Methods of T-gate fabrication using a hybrid resist

Semiconductor with nanoscale features

Method for forming cornered images on a substrate and photomask formed thereby

Method of assembling a plurality of semiconductor devices having different thickness

Borderless gate structures

Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage

Method for increasing the capacitance of a semiconductor capacitors

Hybrid resist based on photo acid/photo base blending

Trench storage dynamic random access memory cell with vertical transfer device

Dram cell with three-sided-gate transfer device

Frequency doubling hybrid photoresist having negative and positive tone components and method of preparing the same

Method for making a five square vertical DRAM cell

Method for making a DRAM cell with grooved transfer device

Method for forming features using frequency doubling hybrid resist and device formed thereby

High performance MOSFET device with raised source and drain

Fabrication method for high-capacitance storage node structures

Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells

Method for a controlled bottle trench for a dram storage node

Method for forming cornered images on a substrate and photomask formed thereby

Sub-lithographic imaging techniques and processes

Chemical and particulate filters containing chemically modified carbon nanotube structures

Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM

Non-volatile switching and memory devices using vertical nanotubes

Sidewall image transfer (SIT) technologies

Low-k dielectric layer based upon carbon nanostructures

Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions

Patterned SOI by oxygen implantation and annealing

Method of manufacturing dual gate logic devices

Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor

Method of producing an integrated circuit chip using frequency doubling hybrid photoresist and apparatus formed thereby

Method for manufacturing a field effect transitor (FET) having mis-aligned-gate structure

Trench storage DRAM cell with vertical three-sided transfer device

Process for making a DRAM cell with three-sided gate transfer

Method for making oxide

Integrated circuit chip produced by using frequency doubling hybrid photoresist

Process for self-alignment of sub-critical contacts to wiring

Method for forming features using frequency doubling hybrid resist and device formed thereby

Method for forming features using self-trimming by selective etch and device formed thereby

Method for manufacturing high performance MOSFET device with raised source and drain

Formation of out-diffused bitline by laser anneal