Inventor

SRINIVASAN VENKATA NARAYANAN

IN37 patents

⚠️ This page may combine multiple inventors who share the name “SRINIVASAN VENKATA NARAYANAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SRINIVASAN VENKATA NARAYANAN

ST MICROELECTRONICS INT NV

Testing of power on reset (POR) and unmaskable voltage monitors

Isolation enable test coverage for multiple power domains

Circuit and method for scan testing

Testing of power on reset (POR) and unmaskable voltage monitors

Test circuit for dynamic checking for faults on functional and BIST clock paths to memory in both ATPG and LBIST modes

System and method for parallel testing of electronic device

System and method for testing voltage monitors

Voltage level monitoring of an integrated circuit for production test and debug

Logic built-in self-test (LBIST) with pipeline scan enable launch on shift (LOS) flip-flop circuit

Scan circuit and method

Methods and devices for bypassing a voltage regulator

Isolation logic test circuit and associated test method

Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit

Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit

Reset and safe state logic generation in dual power flow devices

Combinatorial serial and parallel test access port selection in a JTAG interface

Sequential test access port selection in a JTAG interface

Sequential test access port selection in a JTAG interface

System and method for parallel testing of electronic device

Voltage regulator bypass circuitry usable during device testing operations

PORs testing in multiple power domain devices

Area, cost, and time-effective scan coverage improvement

ATPG testing method for latch based memories, for area reduction

ATPG testing method for latch based memories, for area reduction

ATPG testing method for latch based memories, for area reduction

Scan circuit and method

Test pattern generation using multiple scan enables

TVF transition coverage with self-test and production-test time reduction

Self-test controller, and associated method

Combinatorial serial and parallel test access port selection in a JTAG interface

Stuck-at fault detection on the clock tree buffers of a clock source

Automatic test pattern generation circuitry in multi power domain system on a chip

Power reduction and effective timing exceptions handling in at-speed capture

Reset and safe state logic generation in dual power flow devices

Circuitry for testing non-maskable voltage monitor for power management block

STMICROELECTRONICS INT NV

Test circuit for electronic device permitting interface control between two supply stacks in a production test of the electronic device

SRINIVASAN VENKATA NARAYANAN

Integrated device test circuits and methods