Stuck-at fault detection on the clock tree buffers of a clock source

Abstract

A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).

What is claimed is: 
     
       1. A circuit, comprising:
 a first clock source generating a first clock signal; 
 a first clock tree through which the first clock signal propagates; 
 a second clock source generating a second clock signal; 
 a second clock tree through which the second clock signal propagates; 
 a multiplexer circuit having a first input coupled to an output of the first clock tree and a second input coupled to an output of the second clock tree; 
 a non-scan flip flop having a data input coupled to receive an input signal and a clock input coupled to the output of the second clock tree; and 
 a scan chain having a first scan flip flop with a data input coupled to an output of the non-scan flip flop, a scan input coupled to a test input and a clock input coupled to an output of the multiplexer. 
 
     
     
       2. The circuit of  claim 1 , wherein the scan chain further includes:
 a combinatorial logic cell having an input coupled to a data output of the first scan flip flop; and 
 a second scan flip flop with a data input coupled to an output of the combinatorial logic cell, a scan input coupled to a scan output of the first scan flip flop and a clock input coupled to the output of the multiplexer. 
 
     
     
       3. The circuit of  claim 1 , wherein the non-scan flip flop further includes a reset input, said non-scan flip flop configured to reset the output of the non-scan flip flop to a reset logic state in response to a reset signal received at the reset input. 
     
     
       4. The circuit of  claim 3 , further including a reset circuit configured to generate the reset signal in advance of a testing operation. 
     
     
       5. The circuit of  claim 4 , further including a control circuit configured to control operation of the multiplexer circuit to pass the first clock signal output of the multiplexer during the testing operation. 
     
     
       6. The circuit of  claim 5 , wherein the first scan flip flop of the scan chain is configured to respond to the passed first clock signal output of the multiplexer by capturing the output of the non-scan flip flop. 
     
     
       7. The circuit of  claim 6 , wherein the captured output of the non-scan flip flop has the reset logic state which indicates detection of a stuck-at fault condition of the second clock tree and has a logic state of the input signal which indicates detection of a no stuck-at fault condition of the second clock tree. 
     
     
       8. The circuit of  claim 1 , wherein the first clock source is an automated test pattern generator (ATPG) clock source and the second clock source is a non-ATPG clock source. 
     
     
       9. The circuit of  claim 1 , wherein the first scan flip flop of the scan chain is configured to respond to a scan clock signal output by the multiplexer by capturing the output of non-scan flip flop. 
     
     
       10. The circuit of  claim 8 , wherein the captured output of the non-scan flip flop has a reset logic state which indicates detection of a stuck-at fault condition of the second clock tree and has a logic state associated with the input signal which indicates detection of a no stuck-at fault condition of the second clock tree. 
     
     
       11. A circuit, comprising:
 a first clock circuit configured to generate a first clock signal; 
 a second clock circuit configured to generate a second clock signal; 
 a multiplexer circuit having a first input coupled to receive the first clock signal and a second input coupled to receive the second clock signal; 
 a non-scan flip flop having a data input coupled to receive an input signal and a clock input coupled to receive the second clock signal; and 
 a scan chain having a first scan flip flop with a data input coupled to an output of the non-scan flip flop, a scan input coupled to receive a test input and a clock input coupled to receive a scan clock signal output from the multiplexer. 
 
     
     
       12. The circuit of  claim 11 , wherein the scan chain further includes:
 a combinatorial logic cell having an input coupled to a data output of the first scan flip flop; and 
 a second scan flip flop with a data input coupled to an output of the combinatorial logic cell, a scan input coupled to a scan output of the first scan flip flop and a clock input coupled to the output of the multiplexer. 
 
     
     
       13. The circuit of  claim 11 , wherein the multiplexer is configured to selectively pass one of the first clock signal and second clock signal to provide the scan clock signal. 
     
     
       14. The circuit of  claim 13 , wherein the first clock signal is selectively passed during a testing operation and the first scan flip flop of the scan chain is configured to respond to the scan clock signal by capturing the output of non-scan flip flop. 
     
     
       15. The circuit of  claim 14 , wherein the captured output of the non-scan flip flop has a first logic state associated with the input signal which indicates detection of a no stuck-at fault condition of the second clock circuit and has a second logic state which indicates detection of a stuck-at fault condition of the second clock circuit. 
     
     
       16. The circuit of  claim 14 , wherein the non-scan flip flop further includes a reset input, said non-scan flip flop configured to reset the output of the non-scan flip flop to a reset logic state in response to a reset signal received at the reset input prior to said testing operation. 
     
     
       17. The circuit of  claim 11 , wherein the first clock circuit includes an automated test pattern generator (ATPG) clock source and the second clock circuit includes a non-ATPG clock source. 
     
     
       18. The circuit of  claim 11 , wherein the first clock circuit includes a first plurality of buffer circuits and the second clock circuit includes a second plurality of buffer circuits. 
     
     
       19. The circuit of  claim 18 , wherein the first scan flip flop of the scan chain is configured to respond to the scan clock signal by capturing the output of non-scan flip flop, and wherein the captured output of the non-scan flip flop has a first logic state associated with the input signal which indicates detection of a no stuck-at fault condition within the second plurality of buffer circuits and has a second logic state which indicates detection of a stuck-at fault condition within the second plurality of buffer circuits. 
     
     
       20. The circuit of  claim 11 , wherein the input signal is a fixed logic state signal. 
     
     
       21. The circuit of  claim 1 , wherein the input signal is a fixed logic state signal. 
     
     
       22. A circuit, comprising:
 a first clock source generating a first clock signal; 
 a first clock tree through which the first clock signal propagates; 
 a second clock source generating a second clock signal; 
 a second clock tree through which the second clock signal propagates; 
 a multiplexer circuit having a first input coupled to receive the first clock signal from the first clock tree and a second input coupled to receive the second clock signal from the second clock tree, the multiplexer configured to output a scan clock signal; 
 a non-scan flip flop having a data input coupled to receive a signal at fixed first logic state, a reset input coupled to receive a reset control signal, and a clock input coupled to receive the second clock signal, said non-scan flip flop configured to generate an output signal in response to the second clock signal, said output signal having the first logic state when the reset control signal is deasserted and having a fixed second logic state when the reset control signal is asserted; and 
 a scan chain having a first scan flip flop with a data input coupled to receive the output signal from the non-scan flip flop, a scan input coupled to receive a test data signal, a clock input coupled to receive the scan clock signal and a scan enable input coupled to receive a scan enable signal, the first scan flip flop configured to couple the scan input to both a data input and a scan output of the first scan flip flop in response to deassertion of the scan enable signal and to couple the data input to both the data input and the scan output of the first scan flip flop in response to deassertion of the scan enable signal.