Inventor · disambiguated record
Venkata Narayanan Srinivasan
Also filed as: SRINIVASAN VENKATA NARAYANAN
36 granted patents·2 pending applications·99 citations·filing 2011–2024
96Inventor score
Top patents by PatentIndex Score
38 records- 0198US11119153B1Isolation enable test coverage for multiple power domainsST MICROELECTRONICS INT NV·Filed 2020·Granted Sep 14, 2021·11 cites·20 claims
- 0295US9698771B1Testing of power on reset (POR) and unmaskable voltage monitorsST MICROELECTRONICS INT NV·Filed 2016·Granted Jul 4, 2017·24 cites·26 claims
- 0393US11714131B1Circuit and method for scan testingST MICROELECTRONICS INT NV·Filed 2022·Granted Aug 1, 2023·7 cites·20 claims
- 0493US11442108B1Isolation logic test circuit and associated test methodST MICROELECTRONICS INT NV·Filed 2021·Granted Sep 13, 2022·4 cites·24 claims
- 0590US11550348B2Methods and devices for bypassing a voltage regulatorST MICROELECTRONICS INT NV·Filed 2021·Granted Jan 10, 2023·3 cites·22 claims
- 0690US10996266B2System and method for testing voltage monitorsST MICROELECTRONICS INT NV·Filed 2019·Granted May 4, 2021·4 cites·25 claims
- 0789US11726140B2Scan circuit and methodST MICROELECTRONICS INT NV·Filed 2021·Granted Aug 15, 2023·2 cites·21 claims
- 0889US11340292B2System and method for parallel testing of electronic deviceST MICROELECTRONICS INT NV·Filed 2019·Granted May 24, 2022·3 cites·20 claims
- 0988US11513544B1Reset and safe state logic generation in dual power flow devicesST MICROELECTRONICS INT NV·Filed 2021·Granted Nov 29, 2022·4 cites·20 claims
- 1088US10393804B2Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuitST MICROELECTRONICS INT NV·Filed 2018·Granted Aug 27, 2019·4 cites·17 claims
- 1188US9941875B2Testing of power on reset (POR) and unmaskable voltage monitorsST MICROELECTRONICS INT NV·Filed 2017·Granted Apr 10, 2018·6 cites·11 claims
- 1286US12146911B1TVF transition coverage with self-test and production-test time reductionST MICROELECTRONICS INT NV·Filed 2023·Granted Nov 19, 2024·1 cites·20 claims
- 1383US12399218B2PORs testing in multiple power domain devicesST MICROELECTRONICS INT NV·Filed 2023·Granted Aug 26, 2025·1 cites·20 claims
- 1482US10802077B1Test circuit for dynamic checking for faults on functional and BIST clock paths to memory in both ATPG and LBIST modesST MICROELECTRONICS INT NV·Filed 2019·Granted Oct 13, 2020·10 cites·15 claims
- 1580US10502784B2Voltage level monitoring of an integrated circuit for production test and debugST MICROELECTRONICS INT NV·Filed 2017·Granted Dec 10, 2019·3 cites·26 claims
- 1678US10228420B2Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuitST MICROELECTRONICS INT NV·Filed 2016·Granted Mar 12, 2019·3 cites·22 claims
- 1776US10386411B2Sequential test access port selection in a JTAG interfaceST MICROELECTRONICS INT NV·Filed 2017·Granted Aug 20, 2019·1 cites·12 claims
- 1876US10151797B2Logic built-in self-test (LBIST) with pipeline scan enable launch on shift (LOS) flip-flop circuitST MICROELECTRONICS INT NV·Filed 2016·Granted Dec 11, 2018·2 cites·16 claims
- 1975US12272416B2ATPG testing method for latch based memories, for area reductionST MICROELECTRONICS INT NV·Filed 2024·Granted Apr 8, 2025·0 cites·15 claims
- 2074US12203982B2System and method for parallel testing of electronic deviceST MICROELECTRONICS INT NV·Filed 2022·Granted Jan 21, 2025·0 cites·20 claims
- 2170US12360161B2Scan circuit and methodST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 15, 2025·0 cites·20 claims
- 2270US12020760B2ATPG testing method for latch based memories, for area reductionST MICROELECTRONICS INT NV·Filed 2022·Granted Jun 25, 2024·0 cites·20 claims
- 2370US10747282B2Test circuit for electronic device permitting interface control between two supply stacks in a production test of the electronic deviceSTMICROELECTRONICS INT NV·Filed 2018·Granted Aug 18, 2020·2 cites·21 claims
- 2467US12366605B2Area, cost, and time-effective scan coverage improvementST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 22, 2025·0 cites·20 claims
- 2567US10890619B2Sequential test access port selection in a JTAG interfaceST MICROELECTRONICS INT NV·Filed 2019·Granted Jan 12, 2021·0 cites·19 claims
- 2666US11041905B2Combinatorial serial and parallel test access port selection in a JTAG interfaceST MICROELECTRONICS INT NV·Filed 2019·Granted Jun 22, 2021·0 cites·15 claims
- 2766US9335375B2Integrated device test circuits and methodsSRINIVASAN VENKATA NARAYANAN·Filed 2011·Granted May 10, 2016·3 cites·26 claims
- 2865US12345764B2Test pattern generation using multiple scan enablesST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 1, 2025·0 cites·20 claims
- 2964US11557364B1ATPG testing method for latch based memories, for area reductionST MICROELECTRONICS INT NV·Filed 2021·Granted Jan 17, 2023·0 cites·19 claims
- 3063US10527672B2Voltage regulator bypass circuitry usable during device testing operationsST MICROELECTRONICS INT NV·Filed 2017·Granted Jan 7, 2020·1 cites·21 claims
- 3161US10495690B2Combinatorial serial and parallel test access port selection in a JTAG interfaceST MICROELECTRONICS INT NV·Filed 2017·Granted Dec 3, 2019·0 cites·10 claims
- 3254US2025370529A1Power supply selectionST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 3352US11835991B2Self-test controller, and associated methodST MICROELECTRONICS INT NV·Filed 2021·Granted Dec 5, 2023·0 cites·26 claims
- 3452US10048315B2Stuck-at fault detection on the clock tree buffers of a clock sourceST MICROELECTRONICS INT NV·Filed 2016·Granted Aug 14, 2018·0 cites·22 claims
- 3549US10620267B2Circuitry for testing non-maskable voltage monitor for power management blockST MICROELECTRONICS INT NV·Filed 2017·Granted Apr 14, 2020·0 cites·26 claims
- 3648US11680982B2Automatic test pattern generation circuitry in multi power domain system on a chipST MICROELECTRONICS INT NV·Filed 2021·Granted Jun 20, 2023·0 cites·17 claims
- 3748US2025070785A1Method to test synchronous domains during stuck-at testST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 3847US11983025B2Reset and safe state logic generation in dual power flow devicesST MICROELECTRONICS INT NV·Filed 2022·Granted May 14, 2024·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →