Inventor

KEIL SHANE J

US35 patents

⚠️ This page may combine multiple inventors who share the name “KEIL SHANE J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KEIL SHANE J

APPLE INC

System on a chip with always-on processor

Memory arbitration techniques based on latency tolerance

System on a chip with always-on processor

System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode

System on a chip with always-on processor

System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode

Method for asynchronous gating of signals between clock domains

Write/read turn techniques based on latency tolerance

Method and apparatus of emulating interfaces using FIFOs

Method for synchronizing independent clock signals

Dynamic clock and power gating with decentralized wake-ups

Memory access scheduling using category arbitration

System and method for performing per-bank memory refresh

Write arbiter circuit with per-rank allocation override mode

System on a chip with always-on processor

Memory device bandwidth optimization

System on a chip with always-on component with powered-down configurations to process audio samples

Memory device bandwidth optimization

Multi-activation techniques for partial write operations

Scheduling of read and write memory access requests

Memory bank hotspotting

Ordering memory requests based on access efficiency

Numerically-controlled oscillator

Reset extender for divided clock domains

Read arbiter circuit with dual memory rank support

Ordering memory requests based on access efficiency

Interface emulator using FIFOs

Clock generation using fixed dividers and multiplex circuits

Interfacing dynamic hardware power managed blocks and software power managed blocks

Interfacing dynamic hardware power managed blocks and software power managed blocks

Selectively permitting an apparatus to be awakened depending on a programmable setting

Slow to fast clock synchronization

Memory access scheduling using a linked list

System and method for communication link management in a credit-based system

NVIDIA CORP

Zero frame buffer