Inventor

DE INDRANIL

US115 patents

⚠️ This page may combine multiple inventors who share the name “DE INDRANIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DE INDRANIL

PDF SOLUTIONS INC

E-beam inspection apparatus and method of using the same on various integrated circuit chips

Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads

Integrated circuit containing DOEs of NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells

IC with test structures and E-beam pads embedded within a contiguous standard cell area

Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells

Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells

Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells

Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Process for making and using mesh-style NCEM pads

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells

Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells

Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells

Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate

Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells

Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

KLA TENCOR TECH CORP

Apparatus and methods for detection of systematic defects

Apparatus and methods for determining and localization of failures in test structures using voltage contrast

Electrical defect detection using pre-charge and sense scanning with prescribed delays

INTERMOLECULAR INC

Shadow mask for patterned deposition on substrates

Multi-region processing system and heads

ENDO RICK

Multi-region processing system

KLA TENCOR CORP

Robust measurement of parameters

HASHIM IMRAN

Yttrium and titanium high-k dielectric films

CHENG JEREMY

Substrate processing including correction for deposition location

TIVRA CORP

Multilayer substrate structure and method of manufacturing the same