Inventor

HESS CHRISTOPHER

US121 patents

⚠️ This page may combine multiple inventors who share the name “HESS CHRISTOPHER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HESS CHRISTOPHER

PDF SOLUTIONS INC

E-beam inspection apparatus and method of using the same on various integrated circuit chips

System and method for product yield prediction

System and method for product yield prediction using a logic characterization vehicle

System and method for product yield prediction

Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

System and method for product yield prediction

Designing an integrated circuit to improve yield using a variant design element

Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads

Integrated circuit containing DOEs of NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells

System and method for product yield prediction

System and method for product yield prediction

System and method for product yield prediction

Passive multiplexor test structure for integrated circuit manufacturing

High density test structure array to support addressable high accuracy 4-terminal measurements

Method for improving mask layout and fabrication

IC with test structures and E-beam pads embedded within a contiguous standard cell area

Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells

Test vehicle with zig-zag structures

Test structures for estimating dishing and erosion effects in copper damascene technology

Extraction method of defect density and size distributions

Reusable test chip for inline probing of three dimensionally arranged experiments

Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells

Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells

Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Process for making and using mesh-style NCEM pads

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells

Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells

ACTION TARGET INC

Display screen or portion thereof with graphical user interface

Target system

Walking target

HESS CHRISTOPHER

Method and configuration for connecting test structures or line arrays for monitoring integrated circuit manufacturing

UHDE INVENTA FISCHER GMBH

Method for the production of aliphatic polyesters