Inventor

RANA PARVINDER KUMAR

IN24 patents

⚠️ This page may combine multiple inventors who share the name “RANA PARVINDER KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RANA PARVINDER KUMAR

SAMSUNG ELECTRONICS CO LTD

Method for high performance standard cell design techniques in finFET based library using local layout effects (LLE)

Methods and systems for performing decoding in finFET based memories

Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE)

Sense amplifier flip-flop and method for fixing setup time violations in an integrated circuit

Apparatus and methods for compensating for variations in fabrication process of component(s) in a memory

Circuits for power down leakage reduction in random-access memory

Bitline precharge system for a semiconductor memory device

Bitline precharge system for a semiconductor memory device

Level shifter circuits

Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE)

Memory providing signal buffering scheme for array and periphery signals and operating method of the same

Static random-access memory (SRAM) system with delay tuning and control and a method thereof

Low voltage tolerant ultra-low power edge triggered flip-flop for standard cell library

Flip-flop with single pre-charge node

Static random-access memory with virtual banking architecture, and system and method including the same

Static random-access memory with virtual banking architecture, and system and method including the same

Memory device and operation to reduce impact of parasitic wire resistance and capacitance

System on-chip (SoC) device with dedicated clock generator for memory banks

Methods and apparatuses to reduce power dissipation in a static random access memory (SRAM) device

DENG XIAOWEI

Margin testing of static random access memory cells

SHRIVASTAVA AATMESH

Fast start-up crystal oscillator

JOSHI MANISH CHANDRA

High performance two-port SRAM architecture using 8T high performance single port bit cell

PRASAD RAVI SHANKAR

Voltage compensated tracking circuit in SRAM

TEXAS INSTRUMENTS INC

Automatic latch-up prevention in SRAM